Dual-clock fifo apparatus for packet transmission

Patent metadata

Field	Value
Publication number	US-2016239263-A1
Application number	US-201615015694-A
Country	US
Kind code	A1
Filing date	Feb 4, 2016
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

Disclosed is a dual-clock FIFO apparatus for packet transmission. The FIFO apparatus includes a multi-clock data queue which stores packets and has different read and write clock domains, a packet information queue configured to operate in the write clock domain and to store information data and a tail pointer for the packets, stored in the multi-clock data queue, when writing of packets to the multi-clock data queue is completed, a write state machine configured to operate in the write clock domain, and to read information and pointer data from the packet information queue and notify a read state machine that a packet is ready to read, and the read state machine configured to operate in a read clock domain, to determine whether a packet to be read is ready, and to monitor reading procedure of packet in the multi-clock data queue.

First claim

What is claimed is:

1 . A dual-clock First-In First-Out (FIFO) apparatus for packet transmission, comprising:
a multi-clock data queue configured to store packets and to have different read and write clock domains; a packet information queue configured to operate in the write clock domain and to store information data and a tail pointer (IPD) for the packets, stored in the multi-clock data queue, when writing of packets to the multi-clock data queue is completed; a write state machine configured to operate in the write clock domain, and to read the IPD from the packet information queue and notify a read state machine that a packet is ready to read; and a read state machine configured to operate in a read clock domain, to determine whether a packet to be read is ready, and to monitor reading procedure of packet in the multi-clock data queue.

2 . The dual-clock FIFO apparatus of claim 1 , wherein the multi-clock data queue receives a write error (Write_err) signal when an error is detected while packets are being written and consequently, the corresponding packet is not stored, a write done (Write_done) signal which indicates that the last word of packet has been normally written without an error, and a discard signal that instructs a packet in the queue to be discarded before or while the corresponding packet is read.

3 . The dual-clock FIFO apparatus of claim 2 , wherein when a packet is written to the multi-clock data queue, the write done signal is input to the packet information queue.

4 . The dual-clock FIFO apparatus of claim 3 , wherein:
the write done signal enables the IPD to be written to the packet information queue, and the packet information queue notifies the write state machine that the packet information queue is not empty when the IPD is written to the packet information queue.

5 . The dual-clock FIFO apparatus of claim 4 , wherein the write state machine is configured to, when the packet information queue is not empty, read the IPD from the packet information queue, store the IPD in an IPD register located in the write clock domain, and notify the read state machine that a packet is ready for transmission, through a packet ready register.

6 . The dual-clock FIFO apparatus of claim 5 , wherein the read state machine is configured to, when recognizing that the packet to be read is ready for transmission by means of the value of the packet ready register, store information of the IPD register in an information data register and a tail pointer register that are located in the read clock domain.

7 . The dual-clock FIFO apparatus of claim 6 , wherein:
the value of the tail pointer register is input to the multi-clock data queue, and the multi-clock data queue changes its state to a non-empty state as the value of the tail pointer register has changed, and changes its state to the empty state as the packet is read completely.

8 . The dual-clock FIFO apparatus of claim 7 , wherein the read state machine is configured to, when recognizing that the multi-clock data queue is empty, change the value of the read done register.

9 . The dual-clock FIFO apparatus of claim 8 , wherein the write state machine is configured to, as the read state machine changes the value of the read done register, store a head pointer value of the multi-clock data queue in the head pointer register.

10 . The dual-clock FIFO apparatus of claim 9 , wherein the value stored in the head pointer register is compared with a tail pointer output from the multi-clock data queue.

11 . The dual-clock FIFO apparatus of claim 9 , wherein values delivered between the write clock domain and the read clock domain include the value of the packet ready output from the write state machine, the value of the read done output from read state machine, the value of the IPD register, and the value of the head pointer value from the multi-clock data queue.

12 . The dual-clock FIFO apparatus of claim 11 , wherein each of the packet ready register and the read done register solves metastability using a two-stage register.

13 . The dual-clock FIFO apparatus of claim 12 , wherein the information data register and the tail pointer register are configured such that, even though the values of the information data register and the tail pointer register are not stabilized when the first stage register of the packet ready register has changed, their values are gradually stabilized until the second stage register of the packet ready register is changed.

14 . The dual-clock FIFO apparatus of claim 9 , wherein the multi-clock data queue comprises:
dual-port memory configured to have different write and read clock domains; a tail pointer control unit configured to receive the write error signal and the write done signal and to operate in response to the received signals; and a head pointer control unit configured to receive the discard signal and the value of the tail pointer register located in the read clock domain and to operate in response to the received signal and value.

15 . The dual-clock FIFO apparatus of claim 14 , wherein the tail pointer control unit is configured to, when the write error signal is input, replace a current tail pointer register with a previous tail pointer register, thus discarding a packet that is currently being written.

16 . The dual-clock FIFO apparatus of claim 15 , wherein the tail pointer control unit is configured to, when the write done signal is input, fetch a value from a current tail pointer register and store the value in a previous tail pointer register.

17 . The dual-clock FIFO apparatus of claim 15 , wherein the head pointer control unit is configured to, when the discard signal is input, replace a value of a current head pointer register with the value of the tail pointer register.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Park Chan-Ho

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F5/14 Primary

  for overflow or underflow handling, e.g. full or empty flags · CPC title

• G06F2205/067

  Bidirectional FIFO, i.e. system allowing data transfer in two directions · CPC title

• H04L47/625 Primary

  for service slots or service orders · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title