First-in first-out circuits and methods

Patent metadata

Field	Value
Publication number	US-9330740-B1
Application number	US-201314133245-A
Country	US
Kind code	B1
Filing date	Dec 18, 2013
Priority date	Dec 18, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A first first-in first-out (FIFO) circuit includes a storage circuit, a second first-in first-out (FIFO) circuit, and a third first-in first-out (FIFO) circuit. The storage circuit stores write data at a write address in response to a write clock signal. The storage circuit outputs read data from a read address in response to a read clock signal. A write pointer indicating the write address is synchronized with the write clock signal. A read pointer indicating the read address is synchronized with the read clock signal. The second first-in first-out (FIFO) circuit synchronizes the write pointer with the read clock signal. The third first-in first-out (FIFO) circuit synchronizes the read pointer with the write clock signal.

First claim

What is claimed is:

1. A first first-in first-out circuit comprising:
a first storage circuit to store write data at a write address in response to a write clock signal, the first storage circuit to output read data from a read address in response to a read clock signal, wherein a write pointer indicating the write address is synchronized with the write clock signal, and wherein a read pointer indicating the read address is synchronized with the read clock signal;
a second first-in first-out circuit to synchronize the write pointer with the read clock signal, wherein the second first-in first-out circuit comprises:
a first loop circuit to generate a first read address signal and a first write address signal, and
a second storage circuit to store the write pointer at a first storage location indicated by the first write address signal and to read the write pointer from the first storage location based on the first read address signal; and

a third first-in first-out circuit to synchronize the read pointer with the write clock signal.

2. The first first-in first-out circuit of claim 1 further comprising:
a first comparator circuit to generate a first comparison signal based on a comparison between the write pointer synchronized with the write clock signal and the read pointer synchronized with the write clock signal; and
a second comparator circuit to generate a second comparison signal based on a comparison between the read pointer synchronized with the read clock signal and the write pointer synchronized with the read clock signal.

3. The first first-in first-out circuit of claim 1 , wherein the first loop circuit comprises first metastability harden register circuits and an inverter circuit to generate the first write address signal based on the first read address signal, and wherein the first loop circuit further comprises second metastability harden register circuits to generate the first read address signal based on the first write address signal.

4. The first first-in first-out circuit of claim 3 , wherein the second first-in first-out circuit further comprises:
a logic gate circuit to generate an output signal based on the first read address signal; and
flip-flop circuits to store the write pointer read from the second storage circuit when the flip-flop circuits are enabled by the output signal of the logic gate circuit.

5. The first first-in first-out circuit of claim 1 , wherein the third first-in first-out circuit comprises:
a second loop circuit to generate a second read address signal and a second write address signal; and
a third storage circuit to store the read pointer at a second storage location indicated by the second write address signal and to read the read pointer from the second storage location based on the second read address signal.

6. The first first-in first-out circuit of claim 5 , wherein the second loop circuit comprises first metastability harden register circuits and an inverter circuit to generate the second write address signal based on the second read address signal, and wherein the second loop circuit further comprises second metastability harden register circuits to generate the second read address signal based on the second write address signal.

7. The first first-in first-out circuit of claim 6 , wherein the third first-in first-out circuit further comprises:
a logic gate circuit to generate an output signal based on the second read address signal and based on a second signal generated by the second metastability harden register circuits; and
flip-flop circuits to store the read pointer read from the third storage circuit when the flip-flop circuits are enabled by the output signal of the logic gate circuit.

8. The first first-in first-out circuit of claim 1 further comprising:
a write pointer generator circuit to generate the write pointer; and
a read pointer generator circuit to generate the read pointer.

9. The first first-in first-out circuit of claim 1 , wherein the second first-in first-out circuit comprises a fourth first-in first-out circuit, and wherein the third first-in first-out circuit comprises a fifth first-in first-out circuit.

10. A circuit comprising:
a first storage circuit to store words of write data at write addresses in response to a write clock signal, the first storage circuit to access words of read data from read addresses in response to a read clock signal, wherein the words of read data are read from the first storage circuit in the same order that the words of write data were stored in the first storage circuit, wherein write pointers indicating the write addresses are synchronized with the write clock signal, and wherein read pointers indicating the read addresses are synchronized with the read clock signal;
a second storage circuit to synchronize the write pointers with the read clock signal, wherein the write pointers are read from the second storage circuit in the same order that the write pointers are stored in the second storage circuit;
a first loop circuit to generate a first read address signal and a first write address signal, wherein the second storage circuit stores the write pointers at first storage locations indicated by the first write address signal and accesses the write pointers from the first storage locations based on the first read address signal; and
a third storage circuit to synchronize the read pointers with the write clock signal, wherein the read pointers are read from the third storage circuit in the same order that the read pointers are stored in the third storage circuit.

11. The circuit of claim 10 further comprising:
a first comparator circuit to generate a first comparison signal based on a comparison between the write pointers synchronized with the write clock signal and the read pointers synchronized with the write clock signal;
a second comparator circuit to generate a second comparison signal based on a comparison between the read pointers synchronized with the read clock signal and the write pointers synchronized with the read clock signal;
a write pointer generator circuit to generate the write pointers in response to the write clock signal; and
a read pointer generator circuit to generate the read pointers in response to the read clock signal.

12. The circuit of claim 10 further comprising:
a second loop circuit to generate a second read address signal and a second write address signal,
wherein the third storage circuit stores the read pointers at second storage locations indicated by the second write address signal and accesses the read pointers from the second storage locations based on the second read address signal.

13. The circuit of claim 12 , wherein the first loop circuit comprises first metastability harden register circuits and a first inverter circuit to generate the first write address signal based on the first read address signal, wherein the first loop circuit further comprises second metastability harden register circuits to generate the first read address signal based on the first write address signal,
wherein the second loop circuit comprises third metastability harden register circuits and a second inverter circuit to generate the second write address signal based on the second read address signal, and wherein the second loop circuit further comprises fourth metastability harden register circuits to generate the second read address signal based on the second write address signal.

14. A method comprising:
storing write data in a first storage circuit at a write address in response to a write clock signal, wherein the first storage circuit is part of a first first-in first-out cir

Assignees

• Altera Corp

Inventors

• Baeckler Gregg William
• Mendel David W

Classifications

• G06F5/14 Primary

  for overflow or underflow handling, e.g. full or empty flags · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G06F2205/061

  Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only · CPC title