Package structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016233194-A1
Application number	US-201514986149-A
Country	US
Kind code	A1
Filing date	Dec 31, 2015
Priority date	Feb 6, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.

First claim

What is claimed is:

1 . A method for fabricating a package structure, comprising the steps of:
providing a dielectric layer having a circuit sub-layer, wherein the dielectric layer has a first surface and a second surface opposite to the first surface; disposing an electronic element on the first surface of the dielectric layer, wherein the electronic element is electrically connected to the circuit sub-layer; forming a plurality of conductive posts on the first surface of the dielectric layer, wherein the conductive posts are electrically connected to the circuit sub-layer; and forming an encapsulant on the first surface of the dielectric layer to encapsulate the electronic element and the conductive posts, wherein upper surfaces of the conductive posts are exposed from the encapsulant.

2 . The method of claim 1 , further comprising forming an RDL (Redistribution Layer) structure on the encapsulant, wherein the RDL structure is electrically connected to the conductive posts.

3 . The method of claim 1 , further comprising forming a plurality of conductive elements on the second surface of the dielectric layer, wherein the conductive elements are electrically connected to the circuit sub-layer.

4 . The method of claim 3 , further comprising disposing another electronic element on the conductive elements.

5 . The method of claim 2 , further comprising forming a plurality of conductive elements on the second surface of the dielectric layer, wherein the conductive elements are electrically connected to the circuit sub-layer.

6 . The method of claim 5 , further comprising disposing another electronic element on the conductive elements.

7 . The method of claim 1 , further comprising disposing another electronic element on the conductive posts exposed from the encapsulant.

8 . The method of claim 2 , further comprising disposing another electronic element on the RDL structure.

9 . The method of claim 2 , wherein the RDL structure at least has a circuit sub-layer.

10 . The method of claim 9 , further comprising forming an insulating layer on the RDL structure, wherein the insulating layer has a plurality of openings exposing the circuit sub-layer of the RDL structure.

11 . The method of claim 1 , wherein the circuit sub-layer has a second metal layer and a first metal layer formed on the first surface and the second surface of the dielectric layer, respectively.

12 . The method of claim 11 , wherein the first metal layer and the second metal layer serve as UBM (Under Bump Metallurgy) layers.

13 . The method of claim 1 , after disposing the electronic element on the first surface of the dielectric layer, further comprising forming an underfill between the electronic element and the dielectric layer.

14 . The method of claim 1 , wherein forming the dielectric layer having the circuit sub-layer comprises:
forming a first dielectric layer on a surface of a carrier, wherein the first dielectric layer has a plurality of first openings exposing portions of the surface of the carrier; forming a first metal layer on the first dielectric layer and in the first openings of the first dielectric layer; forming a first resist layer on the first metal layer, wherein the first resist layer has a plurality of open areas exposing portions of the first metal layer on the first dielectric layer and in the first openings; forming a circuit sub-layer on the first metal layer in the open areas of the first resist layer; and removing the first resist layer and the first metal layer under the first resist layer.

15 . The method of claim 14 , wherein the circuit sub-layer has a plurality of conductive bumps formed thereon, forming the conductive bumps comprising:
forming a second dielectric layer on the first dielectric layer and the circuit sub-layer, wherein the second dielectric layer has a plurality of second openings exposing portions of the circuit sub-layer; forming a second metal layer on the second dielectric layer and in the second openings of the second dielectric layer; forming a second resist layer on the second metal layer, wherein the second resist layer has a plurality of open areas exposing portions of the second metal layer in the second openings and around peripheries of the second openings; forming conductive bumps on the second metal layer in the open areas of the second resist layer, wherein the conductive bumps are electrically connected to the circuit sub-layer; and removing the second resist layer.

16 . The method of claim 15 , wherein the circuit sub-layer has a plurality of conductive posts formed thereon, forming the conductive posts comprising:
forming a third resist layer on the second metal layer and the conductive bumps, wherein the third resist layer has a plurality of open areas exposing portions of the second metal layer; and forming conductive posts on the second metal layer in the open areas of the third resist layer, wherein the conductive posts are electrically connected to the circuit sub-layer.

17 . The method of claim 16 , wherein the circuit sub-layer has a plurality of conductive elements formed thereon, forming the conductive elements comprising:
removing the carrier so as to expose portions of the first metal layer from the first dielectric layer; and forming conductive elements on the exposed portions of the first metal layer.

18 . The method of claim 1 , wherein the dielectric layer has a plurality of conductive bumps formed on the first surface thereof and electrically connected to the circuit sub-layer for disposing the electronic element.

19 . The method of claim 1 , after forming the encapsulant, further comprising thinning the encapsulant to expose the upper surfaces of the conductive posts or expose both the upper surfaces of the conductive posts and a surface of the electronic element.

20 . A package structure, comprising:
a dielectric layer having a first surface and a second surface opposite to the first surface; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts, wherein upper surfaces of the conductive posts are exposed from the encapsulant.

21 . The structure of claim 20 , further comprising an RDL structure formed on the encapsulant and electrically connected to the conductive posts.

22 . The structure of claim 21 , further comprising an insulating layer formed on the RDL structure.

23 . The structure of claim 21 , further comprising another electronic element disposed on the RDL structure.

24 . The structure of claim 20 , wherein a plurality of conductive bumps are formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer for disposing the electronic element.

25 . The structure of claim 20 , further comprising a plurality of conductive elements formed on the second surface of the dielectric layer and electrically connected to the circuit sub-layer.

26 . The structure of claim 25 , further comprising another electronic element disposed on the conducti

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Chen Lu-Yi
• Lu Chang-Lun
• Chen Shih-Ching
• Ma Guang-Hwa
• Hsiao Cheng-Hsu

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title