Electronic device and method for manufacturing the same

US2016233181A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016233181-A1
Application numberUS-201614994529-A
CountryUS
Kind codeA1
Filing dateJan 13, 2016
Priority dateFeb 6, 2015
Publication dateAug 11, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device includes a first electronic component including a first electrode, a solder provided above the first electrode, and a first bonding layer provided between the first electrode and the solder and containing Pd, Ag, and In. In another aspect of the invention, a method for manufacturing an electronic device, the method includes providing a solder containing In and Ag above a layer containing Pd and provided above an electrode of an electronic component; and melting the solder by heating to form a bonding layer containing Pd, Ag, and In between the electrode and the solder.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic device comprising: a first electronic component including a first electrode; a solder provided above the first electrode; and a first bonding layer provided between the first electrode and the solder and containing Pd, Ag, and In. 2 . The electronic device according to claim 1 , wherein the first bonding layer includes a first layer provided above the first electrode and containing Pd and Ag, and a second layer provided above the first layer and containing In. 3 . The electronic device according to claim 2 , wherein the first layer contains Pd as a primary component. 4 . The electronic device according to claim 2 , wherein the first layer is a PdAg alloy layer or a PdAgIn alloy layer. 5 . The electronic device according to claim 2 , wherein the second layer contains In as a primary component. 6 . The electronic device according to claim 2 , wherein the second layer is an InAu alloy layer or an InAuPd alloy layer. 7 . The electronic device according to claim 1 , wherein the first electrode contains Cu or Ni, and the solder contains Sn. 8 . The electronic device according to claim 1 , wherein the first electrode includes an electrode layer, and a barrier metal layer provided above the electrode layer. 9 . The electronic device according to claim 1 , further comprising: a second electronic component including a second electrode which faces the first electrode with the solder interposed therebetween; and a second bonding layer provided between the solder and the second electrode and containing Pd, Ag, and In. 10 . A method for manufacturing an electronic device, the method comprising: providing a solder containing In and Ag above a layer containing Pd and provided above an electrode of an electronic component; and melting the solder by heating to form a bonding layer containing Pd, Ag, and In between the electrode and the solder. 11 . The method for manufacturing an electronic device according to claim 10 , wherein the providing a solder includes providing the solder above the layer containing Pd with a layer containing Au interposed therebetween. 12 . A method for manufacturing an electronic device, the method comprising: providing a solder above a layer containing In and provided above an electrode of an electronic component with a layer containing Pd and Ag interposed therebetween; and melting the solder by heating to form a bonding layer containing Pd, Ag, and In between the electrode and the solder. 13 . The method for manufacturing an electronic device according to claim 12 , wherein the layer containing In contains In and Au. 14 . The method for manufacturing an electronic device according to claim 10 , wherein the bonding layer includes a first layer provided above the electrode and containing Pd and Ag, and a second layer provided above the first layer and containing In.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • changes in materials · CPC title

  • Soldering or alloying · CPC title

  • Intermetallic compounds · CPC title

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What does patent US2016233181A1 cover?
An electronic device includes a first electronic component including a first electrode, a solder provided above the first electrode, and a first bonding layer provided between the first electrode and the solder and containing Pd, Ag, and In. In another aspect of the invention, a method for manufacturing an electronic device, the method includes providing a solder containing In and Ag above a la…
Who is the assignee on this patent?
Fujitsu Ltd
What technology area does this patent fall under?
Primary CPC classification H10W72/012. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 11 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).