Power semiconductor device

Patent metadata

Field	Value
Publication number	US-2016233151-A1
Application number	US-201415021413-A
Country	US
Kind code	A1
Filing date	Jan 10, 2014
Priority date	Jan 10, 2014
Publication date	Aug 11, 2016
Grant date	—

Abstract

An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface.

First claim

1 . A power semiconductor device comprising:
a leadframe; a power semiconductor element disposed on a first main surface of said leadframe; and an insulating member disposed on a second main surface, opposite to said first main surface, of said leadframe, wherein at least a partial line of an insulating region peripheral line is aligned, in top view, with at least a partial line of an expanded peripheral line, said insulting region peripheral line being a peripheral line of a region where said insulting member is disposed, on said second main surface, said expanded peripheral line being obtained by shifting outwardly, by an amount corresponding to a thickness of said leadframe, a peripheral line of a region where said semiconductor element is disposed, on said first main surface.

2 . The power semiconductor device according to claim 1 , wherein
when only the partial line of said insulating region peripheral line is aligned, in top view, with only the partial line of said expanded peripheral line, a remaining line of said insulating region peripheral line is positioned, in top view, outside a remaining line of said expanded peripheral line.

3 . The power semiconductor device according to claim 1 , wherein
said one insulating member is disposed on said second main surface of said one leadframe while corresponding to all of a plurality of said semiconductor elements disposed on said one leadframe, and said expanded peripheral line is obtained by shifting outwardly, by the amount corresponding to the thickness of said leadframe, a peripheral line of a region where all of said plurality of semiconductor elements are disposed, on said first main surface.

4 . The power semiconductor device according to claim 1 , wherein
a plurality of said insulating members are disposed on said second main surface of said one leadframe while corresponding one-to-one to a plurality of said semiconductor elements disposed on said one leadframe.

5 . The power semiconductor device according to claim 1 , wherein
said one insulating member is disposed on said second main surfaces of a plurality of said leadframes while corresponding to all of a plurality of said semiconductor elements in row units disposed on said plurality of leadframes, and said expanded peripheral line is obtained by shifting outwardly, by the amount corresponding to the thickness of said leadframes, a peripheral line of a region where all of said plurality of semiconductor elements in the row units are disposed, on said first main surfaces of said plurality of leadframes.

6 . The power semiconductor device according to claim 1 , wherein
a plurality of said insulating members are disposed on said second main surfaces of a plurality of said leadframes while corresponding one-to-one to a plurality of said semiconductor elements in row units disposed on said plurality of leadframes, and said expanded peripheral line is obtained by shifting outwardly, by the amount corresponding to the thickness of said leadframes, a peripheral line of a region where said semiconductor elements in a corresponding row unit are disposed, on said first main surface of each of said leadframes.

7 . The power semiconductor device according to claim 1 , wherein
an end of said leadframe is bent from a side of said insulating member to a side of said semiconductor element.

8 . The power semiconductor device according to claim 1 , wherein
a through-hole that passes through said first main surface at a location where said semiconductor element is not disposed and through said second main surface at a location where said insulating member is not disposed is provided in said leadframe.

Assignees

• Mitsubishi Electric Corp

Inventors

• Ichikawa Keitaro
• Shikano Taketoshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753 Primary

  between laterally-adjacent chips · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/527

  Multiple bond wires having different sizes · CPC title