Power semiconductor module and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9252028-B2
Application number	US-201514796843-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Nov 15, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion.

First claim

What is claimed is:

1. A method of manufacturing a power semiconductor module, comprising the steps of:
preparing a frame having a first frame portion having a first end surface, a second frame portion having a second end surface facing said first end surface with a gap interposed therebetween, and a third frame portion arranged on respective side portions of said first frame portion and said second frame portion with a gap interposed therebetween and coupling said first frame portion and said second frame portion;
bending said first frame portion and said second frame portion with respect to said third frame portion in a direction crossing a surface of said third frame portion, and shrinking said third frame portion in a direction in which said first end surface and said second end surface face each other;
mounting a power semiconductor element on said first frame portion;
mounting a control integrated circuit for controlling said power semiconductor element on said second frame portion; and
using a wire having one end and the other end to connect said one end to said power semiconductor element and connect the other end to said control integrated circuit.

Assignees

• Mitsubishi Electric Corp

Inventors

• Shiramizu Masataka
• Shang Ming

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title