System and method for error detection of executed program code employing compressed instruction signatures

Patent metadata

Field	Value
Publication number	US-2016232050-A1
Application number	US-201615014251-A
Country	US
Kind code	A1
Filing date	Feb 3, 2016
Priority date	Feb 5, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode. Moreover, the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

First claim

1 . A system, comprising:
a first processorconfigured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code; wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode; wherein the first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block; and wherein the first processoris configured to determine that a first error occurred, if the determined error code is different from the stored error code; and a second processor, wherein the second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode; wherein the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

2 . A system according to claim 1 , wherein the second processor is configured to execute the current opcode or a control signal depending on the current opcode, if the second determined signature for the current opcode is not different from the first determined signature for the current opcode.

3 . A system according to claim 1 ,
wherein, for each opcode of the plurality of opcodes, the first processor is configured to decode said opcode to obtain a control signal for said opcode, said control signal being one of a plurality of control signals, wherein the plurality of control signals comprises the control signal depending on the current opcode; and wherein, for each opcode of the plurality of opcodes, the first processor is configured to determine the first determined signature of said opcode depending on the control signal of said opcode.

4 . A system according to claim 3 ,
wherein the first processor comprises a first instruction decoder, an error code generator and a first comparator; wherein, for each opcode of the plurality of opcodes, the first instruction decoder is configured to decode said opcode to obtain the control signal for said opcode, wherein the error code generator is configured to determine the determined error code for the instruction block using the control signal of each opcode of the plurality of opcodes of the instruction block; and wherein the first comparator is configured to determine that the first error occurred, if the determined error code is different from the stored error code.

5 . A system according to claim 3 ,
wherein the system comprises a second memory; wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to store the said opcode or the control signal depending on said opcode into the second memory and is configured to store the first determined signature for said opcode into the second memory; and wherein the second processor is configured to load the current opcode or the control signal depending on the current opcode from the second memory and is configured to load the first determined signature for the current opcode from the second memory.

6 . A system according to claim 5 , wherein the second memory is a cache.

7 . A system according to claim 5 ,
wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to store said opcode into the second memory; wherein the second processor comprises a second instruction decoder, a first signature determiner, a second comparator and a first arithmetic logic unit; wherein the second instruction decoder is configured to load the current opcode from the second memory and to decode the current opcode to obtain the control signal of the current opcode; wherein the first signature determiner is configured to determine the second determined signature for the current opcode using the control signal of the current opcode; wherein the second comparator is configured to load the first determined signature for the current opcode from the second memory; wherein the second comparator is configured to determine that the second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

8 . A system according to claim 5 ,
wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to store the control signal for said opcode into the second memory; wherein the second processor comprises a first signature determiner, a second comparator and a first arithmetic logic unit; wherein the first signature determiner is configured to load the control signal of the current opcode from the second memory, and is configured to determine the second determined signature for the current opcode using the control signal of the current opcode; wherein the second comparator is configured to load the first determined signature for the current opcode from the second memory; wherein the second comparator is configured to determine that the second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

9 . A system according to claim 7 ,
wherein the second processor further comprises a second signature determiner, a third comparator and a second arithmetic logic unit; wherein the second signature determiner is configured to determine a third determined signature for the current opcode using the control signal of the current opcode; wherein the third comparator is configured to determine that a third error occurred, if the third determined signature for the current opcode is different from the first determined signature for the current opcode; and wherein the second arithmetic unit is configured to execute the control signal of the current opcode, if the third determined signature for the current opcode is not different from the first determined signature for the current opcode.

10 . An system according to claim 9 , wherein an execution deviation detector is configured to detect deviating results of the execution of the current opcode or of the execution of the control signal of the current opcode by the first arithmetic logic unit and by the second arithmetic logic unit.

11 . An system according to claim 1 ,
wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine the first determined signature depending on said opcode and depending on a first value for said opcode of a first program counter; wherein the first processor is configured to determine a determined error code for the instruction block depending on each opcode of the plurality of opcodes of the instruction block and depending on the value of the first program counter for each opcode of the plurality of opcodes of the instruction block; wherein the second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode and depending on a second value for said opcode of a second program counter.

12 . A system according to claim 1 ,
wherein the first processor is configured to determine, if the instruction block comprises a partial opcode, wherein said partial opcode is incomplete; wherein, if the partial opcode is located at an end of

Assignees

• Infineon Technologies Ag

Inventors

• Sonnekalb Steffen
• Wenzel Andreas

Classifications

• G06F2212/452

  Instruction code · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title

• G06F11/079 Primary

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title