System and Method for Synchronizing Multiple Oscillators Using Reduced Frequency Signaling

Patent metadata

Field	Value
Publication number	US-2016204784-A1
Application number	US-201514597039-A
Country	US
Kind code	A1
Filing date	Jan 14, 2015
Priority date	Jan 14, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

An embodiment method for voltage-controlled oscillator (VCO) control includes detecting a first VCO output signal of a first VCO. The first VCO output signal has a first VCO output frequency. The method also includes determining a first down-scaled signal in accordance with the first VCO output signal. The first down-scaled signal has a first down-scaled frequency that is reduced by a fixed ratio relative to a current value of the first VCO output frequency. The method also includes modifying the first VCO output frequency using a first phase lock loop (PLL) in accordance with the first down-scaled signal and an oscillating reference signal, and detecting a second VCO output signal of a second VCO. The second VCO output signal has a second VCO output frequency. The method also includes modifying the second VCO output frequency in accordance with the second VCO output signal and the first down-scaled signal.

First claim

What is claimed is:

1 . A method for voltage-controlled oscillator (VCO) control, the method comprising:
detecting a first VCO output signal of a first VCO comprised in a first control circuit, wherein the first VCO output signal has a first VCO output frequency; determining a first down-scaled signal in accordance with the first VCO output signal, wherein the first down-scaled signal has a first down-scaled frequency that is reduced by a fixed ratio relative to a current value of the first VCO output frequency; modifying the first VCO output frequency using a first phase lock loop (PLL) in accordance with the first down-scaled signal and an oscillating reference signal; transmitting the first down-scaled signal over a length of printed circuit board (PCB) from the first control circuit to a second control circuit; detecting a second VCO output signal of a second VCO comprised in the second control circuit, wherein the second VCO output signal has a second VCO output frequency; and modifying the second VCO output frequency in accordance with the second VCO output signal and the first down-scaled signal.

2 . The method of claim 1 , wherein the modifying the first VCO output frequency using the first PLL comprises:
detecting an oscillating reference signal; determining a first error signal in accordance with the oscillating reference signal and the first down-scaled signal, the first error signal comprising at least one of a phase difference and a frequency difference; and modifying the first VCO output frequency in accordance with the first error signal.

3 . The method of claim 2 , wherein the determining the first error signal comprises:
determining a third down-scaled signal having a frequency that is reduced by a fixed ratio relative to a current value of the first down-scaled frequency; band-pass filtering the third down-scaled signal to obtain a band-pass filtered signal; digitally sampling the band-pass filtered signal in accordance with the oscillating reference signal to obtain a digital down-scaled signal; and determining the first error signal in accordance with the digital down-scaled signal.

4 . The method of claim 2 ,
further comprising calculating a tuning signal for a frequency-modulated continuous wave; and wherein the determining the first error signal is further in accordance with the tuning signal.

5 . The method of claim 1 , wherein the modifying the second VCO output frequency comprises:
determining a second down-scaled signal in accordance with the second VCO output signal, wherein the second down-scaled signal has a frequency that is reduced by a fixed ratio relative to the current value of the second output frequency; and modifying the second VCO output frequency using a second PLL in accordance with the second down-scaled signal and the first down-scaled signal.

6 . The method of claim 5 , wherein the modifying the second VCO output frequency using the second PLL comprises:
determining a second error signal in accordance with the first down-scaled signal and the second down-scaled signal, the second error signal comprising at least one of a phase difference and a frequency difference; and modifying the second VCO output frequency in accordance with the second error signal.

7 . The method of claim 5 , wherein the modifying the second VCO output frequency using the second PLL comprises:
adding a first phase delay to the first down-scaled signal to obtain a phase-delayed signal; determining a second error signal in accordance with the phase-delayed signal and the second down-scaled signal, the second error signal comprising at least one of a phase difference and a frequency difference; and modifying the second VCO output frequency in accordance with the second error signal.

8 . The method of claim 7 , further comprising:
transmitting, from a first antenna coupled to the first VCO, a first signal comprised in a radiation pattern; and transmitting, from a second antenna coupled to the second VCO, a second signal comprised in the radiation pattern,
wherein the radiation pattern has a beam axis that is determined in accordance with the first phase delay.

9 . The method of claim 7 further comprising:
calculating a calibration offset;
receiving a desired phase delay; and
subtracting the calibration offset from the desired phase delay to obtain the first phase delay.

10 . A system for voltage-controlled oscillator (VCO) control comprising:
a first VCO having a first control signal and a first VCO output signal, wherein
the first VCO output signal has a first VCO output frequency, and
the first VCO is configured to modify the first VCO output frequency when the first control signal is modified;
a second VCO having a second control signal and a second VCO output signal, wherein
the second VCO output signal has a second VCO output frequency, and
the second VCO is configured to modify the second VCO output frequency when the second control signal is modified;
a second control circuit coupled to the second VCO, wherein the second control circuit is configured to modify the second control signal in accordance with a first down-scaled signal; and a first control circuit coupled to the first VCO and to the second control circuit, wherein
the first control circuit comprises a first frequency down-scaling circuit and a first phase lock loop (PLL) circuit,
the first down-scaled signal has a first down-scaled frequency that is reduced by a fixed ratio relative to a current value of the first VCO output frequency,
the first control circuit is configured to transmit the first down-scaled signal to the second control circuit over a length of printed circuit board (PCB), and
the first PLL circuit is configured to modify the first control signal in accordance with the first down-scaled signal.

11 . The system of claim 10 , wherein
the first frequency down-scaling circuit comprises at least one of a frequency mixer and a frequency divider and is configured to determine the first down-scaled signal in accordance with the first VCO output signal, the first control circuit further comprises an electronic oscillator configured to provide an oscillating reference signal; the first PLL circuit comprises:
a first PLL detector coupled to the first frequency down-scaling circuit and the electronic oscillator; and
a first tuning circuit coupled to the first PLL detector and the first VCO, wherein the first tuning circuit is configured to modify the first control signal in accordance with a first error signal.
the first PLL detector is configured to determine a first error signal in accordance with the oscillating reference signal and the first down-scaled signal, and the first error signal comprises at least one of a phase difference and a frequency difference.

12 . The system of claim 11 , wherein
the tuning circuit comprises a first loop output filter; the first PLL detector is configured to determine the first error signal in accordance with a digital down-scaled signal; and the first PLL circuit further comprises:
a third frequency down-scaling circuit configured to determine a third down-scaled signal having a frequency that is reduced by a fixed ratio relative to a current value of the first down-scaled frequency;
a band-pass filter configured to determine a band-pass filtered signal in accordance with the third down-scaled signal; and
a first analog-to-digital converter (ADC) configured to digitally sample the band-pass filtered signal in accordance with the oscillating reference signal to obtain the digital down-scaled signal.

13 . The system of

Assignees

• Infineon Technologies Ag

Inventors

• Trotta Saverio
• Jungmaier Reinhard-Wolfgang

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H01Q3/30

  varying the {relative} phase {between the radiating elements of an array (H01Q3/2605, H01Q3/2658, H01Q3/2682, H01Q3/44 take precedence)} · CPC title

• H03L7/07 Primary

  using several loops, e.g. for redundant clock signal generation · CPC title