Iii-v mosfet with strained channel and semi-insulating bottom barrier

Patent metadata

Field	Value
Publication number	US-2016204253-A1
Application number	US-201514592130-A
Country	US
Kind code	A1
Filing date	Jan 8, 2015
Priority date	Jan 8, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier. A semi-insulating layer is epitaxially formed on the bottom barrier, laterally adjacent to the channel. The semi-insulating layer is formed in such a way that stress is induced onto the channel. A CMOS transistor is formed on the channel.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a bottom barrier formed on the substrate, wherein the bottom barrier is semi-insulating; a channel formed on the bottom barrier; a gate structure formed on the channel; a source region and a drain region formed laterally adjacent to the gate structure; a semi-insulating layer epitaxially formed laterally adjacent to the channel on the bottom barrier, wherein the semi-insulating layer induces a strain onto the channel;

2 . The semiconductor device of claim 1 , wherein the composition of the semi-insulating layer is selected to change carrier transport properties of the channel.

3 . The semiconductor device of claim 1 , wherein the channel is epitaxially formed on the bottom barrier and the bottom barrier induces a strain onto the channel.

4 . The semiconductor device of claim 1 , wherein the strain is induced by forming a material with a first lattice constant on a material with a second lattice constant.

5 . The semiconductor device of claim 1 , wherein the strain induced onto the channel comprises tension.

6 . The semiconductor device of claim 1 , wherein the strain induced onto the channel comprises compression

7 . The semiconductor device of claim 1 , wherein the semiconductor device is a metal-oxide-semiconductor field effect transistor.

8 . A semiconductor device comprising:
a substrate; a bottom barrier formed on the substrate, wherein the bottom barrier is semi-insulating; a channel epitaxially formed on the bottom barrier, wherein the bottom barrier induces a strain onto the channel; a gate structure formed on the channel; a source region and a drain region formed laterally adjacent to the gate structure; and a semi-insulating layer epitaxially formed laterally adjacent to the channel on the bottom barrier.

9 . The semiconductor device of claim 8 , wherein the composition of the semi-insulating layer is selected to change carrier transport properties of the channel.

10 . The semiconductor device of claim 8 , wherein the strain is induced by forming a material with a first lattice spacing on a material with a second lattice spacing.

11 . The semiconductor device of claim 8 , wherein the strain induced onto the channel comprises tension.

12 . The semiconductor device of claim 8 , wherein the strain induced onto the channel comprises compression.

13 . The semiconductor device of claim 8 , wherein the semiconductor device is a metal-oxide-semiconductor field effect transistor.

14 - 20 . (canceled)

Assignees

• IBM

Inventors

• Basu Anirban
• Cohen Guy
• Majumdar Amlan

Classifications

• H10D62/364

  of IGFETs · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D30/798

  being provided in or under the channel regions · CPC title