Source material for electronic device applications

Patent metadata

Field	Value
Publication number	US-2016204205-A1
Application number	US-201614989097-A
Country	US
Kind code	A1
Filing date	Jan 6, 2016
Priority date	Jan 8, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.

First claim

What is claimed is:

1 . An apparatus, comprising:
a vertical string of memory cells comprising a plurality of alternating levels of conductor material and dielectric material; a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material; and a source material coupled to the conductor material, the source material including a titanium nitride layer, and
a source polysilicon layer in direct contact with the titanium nitride layer.

2 . The apparatus of claim 1 , wherein the titanium nitride layer has a resistivity in the range of about 60 μOhm-cm to about 100 μOhm-cm.

3 . The apparatus of claim 1 , wherein the titanium nitride layer has a resistivity in the range of about 85 μOhm-cm to about 100 μOhm-cm.

4 . The apparatus of claim 1 , wherein the titanium nitride layer has a thickness range from about 100 Å to about 2000 Å.

5 . The apparatus of claim 1 , wherein the source polysilicon layer has a thickness range from about 100 Å to about 2000 Å.

6 . A method, comprising:
forming a source material including a titanium nitride layer and a source layer, the titanium nitride layer being formed on a first side in direct contact with a first side of the source layer; and forming a string of memory cells over the source material, the string of memory cells including a channel material, a first end of the channel material being in contact with a second side of the source material opposing the first side of the source layer, the first side of the source layer being distal to the channel material.

7 . The method of claim 6 , further comprising forming a peripheral support device layer coupled to a second side of the titanium nitride layer, the second side of the titanium nitride layer being distal from the source layer.

8 . The method of claim 7 , further comprising forming a dielectric layer between the titanium nitride layer and the peripheral support device layer.

9 . The method of claim 6 , further comprising forming a metallization contact from the second side of the source layer to a second end of the channel material.

10 . The method of claim 6 , further comprising selecting the source material to comprise doped polysilicon.

11 . A source material for an electronic device, the source material comprising:
a titanium nitride layer having a resistivity in the range of about 60 μOhm-cm to about 100 μOhm-cm; and a source polysilicon layer in direct contact with the titanium nitride layer.

12 . The source material of claim 11 , wherein the titanium nitride layer has a surface roughness range of about 0.4 nm to about 0.6 nm when measured at a spatial bandwidth of about 0.5 μm −1 to about 38.0 μm −1 .

13 . The source material of claim 11 , wherein the titanium nitride layer has a titanium-to-nitrogen ratio of approximately one-to-one.

14 . The source material of claim 11 , wherein the titanium nitride layer has a substantially cubic titanium nitride crystal structure with a {220} orientation.

15 . The source material of claim 11 , wherein the titanium nitride layer has a substantially cubic titanium nitride crystal structure with a {200} orientation.

16 . The source material of claim 11 , wherein the titanium nitride layer is a barrier for dopant migration from the source polysilicon layer.

17 . A method, comprising:
forming a tier layer; forming a semiconductor material extending through the tier layer; forming a source polysilicon layer coupled to the semiconductor material; and forming a titanium nitride layer coupled to the source polysilicon layer without forming a metal silicide layer.

18 . The method of claim 17 , wherein forming the tier layer comprises forming a vertical string of memory cells comprising a plurality of alternating levels of conductor material and dielectric material.

19 . The method of claim 17 , wherein the titanium nitride layer is coupled to the source polysilicon layer without intervening oxides.

20 . A method, comprising:
forming a titanium nitride layer having a resistivity in the range of about 60 μOhm-cm to about 100 μOhm-cm; and forming a source polysilicon layer coupled to the titanium nitride layer.

21 . The method of claim 20 , further comprising forming the source polysilicon layer in direct contact with the titanium nitride layer.

22 . The method of claim 21 , further comprising:
forming a channel material coupled on a first end to the source polysilicon layer; and forming a first metallization contact from a side of the titanium nitride layer that is in contact with the source polysilicon layer to a second end of the channel material.

23 . The method of claim 20 , further comprising forming a second metallization contact from a side of the titanium nitride layer that is opposite the source polysilicon layer to a second end of the channel material.

24 . A method of forming a source material; the method comprising:
forming a titanium nitride layer having a substantially cubic titanium nitride crystal structure with a {220} orientation; and forming a source polysilicon coupled to the titanium nitride layer.

25 . The method of claim 24 , further comprising selecting the titanium nitride layer to have a resistivity less than about 100 μOhm-cm.

Assignees

• Micron Technology Inc

Inventors

• Meldrim John Mark
• Hu Yushi
• Hu Yongjun Jeff
• Mcteer Everett Allen

Classifications

• H10P32/1414 Primary

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/171

  being group IV material · CPC title

• C30B25/02

  Epitaxial-layer growth · CPC title

• C30B23/02

  Epitaxial-layer growth · CPC title

• C30B29/38 Primary

  Nitrides · CPC title