Method for separating substrates and semiconductor chip

US2016204033A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016204033-A1
Application numberUS-201414913681-A
CountryUS
Kind codeA1
Filing dateAug 6, 2014
Priority dateAug 22, 2013
Publication dateJul 14, 2016
Grant date

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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Disclosed is a method for separating a substrate ( 1 ) along a separation pattern ( 4 ), in which method a substrate ( 1 ) is provided and an auxiliary layer ( 3 ) is applied to the substrate, said layer covering the substrate at least along the separation pattern. The substrate comprising the auxiliary layer is irradiated, such that the material of the auxiliary layer penetrates the substrate along the separation pattern in the form of an impurity. The substrate is broken along the separation pattern. A semiconductor chip ( 15 ) is also disclosed.

First claim

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1 . A method for separating a substrate along a separation pattern, comprising the following steps: a) providing the substrate; b) applying an auxiliary layer, which covers the substrate at least along the separation pattern, c) irradiating the substrate with the auxiliary layer, such that material of the auxiliary layer penetrates into the substrate as an impurity along the separation pattern; and d) breaking the substrate along the separation pattern. 2 . The method according to claim 1 , wherein the impurity embrittles the substrate along the separation pattern. 3 . The method according to claim 1 , wherein material of the auxiliary layer indiffuses into the substrate in step c). 4 . The method according to claim 1 , wherein in step c) the substrate melts locally and material of the auxiliary layer is alloyed therein. 5 . The method according to claim 1 , wherein the substrate is metallic. 6 . The method according to claim 1 , wherein the auxiliary layer contains an amide. 7 . The method according to claim 1 , wherein the auxiliary layer contains urea. 8 . The method according to claim 1 , wherein the auxiliary layer is applied to the substrate over the whole area in step b). 9 . The method according to claim 1 , wherein nitrogen is introduced into the substrate as the impurity along the separation pattern. 10 . The method according to claim 1 , wherein the irradiation in step c) is carried out by means of a laser in pulsed operation or in continuous wave operation. 11 . A semiconductor chip comprising a semiconductor body and a metallic substrate body, on which the semiconductor body is arranged, wherein a side surface of the metallic substrate body has a breaking edge. 12 . The semiconductor chip according to claim 11 , wherein the substrate body has, in an edge region adjoining the side surface, a concentration of an impurity that is at least twice as high as that in a region spaced apart from the side surface. 13 . The semiconductor chip according to claim 12 , wherein the impurity is nitrogen. 14 . The semiconductor chip according to claim 11 , wherein the substrate body contains molybdenum. 15 . (canceled) 16 . A semiconductor chip comprising a semiconductor body and a metallic substrate body, on which the semiconductor body is arranged, wherein a side surface of the metallic substrate body has a breaking edge, wherein the substrate body has, in an edge region adjoining the side surface, a concentration of an impurity that is at least twice as high as that in a region spaced apart from the side surface.

Assignees

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Classifications

  • Alloying conductive materials with semiconductor bodies · CPC title

  • with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

  • within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

  • Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

  • characterised by their shape, e.g. having conical or cylindrical projections · CPC title

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What does patent US2016204033A1 cover?
Disclosed is a method for separating a substrate ( 1 ) along a separation pattern ( 4 ), in which method a substrate ( 1 ) is provided and an auxiliary layer ( 3 ) is applied to the substrate, said layer covering the substrate at least along the separation pattern. The substrate comprising the auxiliary layer is irradiated, such that the material of the auxiliary layer penetrates the substrate …
Who is the assignee on this patent?
Osram Opto Semiconductors Gmbh
What technology area does this patent fall under?
Primary CPC classification H10P54/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jul 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).