Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016204010-A1
Application number	US-201615078026-A
Country	US
Kind code	A1
Filing date	Mar 23, 2016
Priority date	Jul 29, 2014
Publication date	Jul 14, 2016
Grant date	—

Abstract

To protect a plurality of semiconductor chips of a sawn wafer housed in a shipping case.
A method of manufacturing a semiconductor device includes a step of vacuum packing a sawn wafer while being housed in a shipping case. The shipping case has the following structure. The shipping case has a lid portion that covers the upper surface of the sawn wafer and a body portion that covers the lower surface of the sawn wafer. The lid portion has a recess portion that covers a plurality of semiconductor chips and a ventilation route communicated with the recess portion. In a step of reducing pressure in the shipping case, a gas in the shipping case is discharged outside via a ventilation route.

First claim

1 - 11 . (canceled)

12 . A case for housing a sawn wafer including a plurality of diced semiconductor chips supported on an adhesive tape attached to a support frame, the case comprising:
a first case portion having a first recessed portion; a second case portion having a second recessed portion; the first and second case portions being detachably attached to each other so as to house the sawn wafer in a space formed by the first and second recessed portions; the first case portion further including a plurality of first support portions positioned outside the first recessed portion so as to support a portion of an upper surface of the sawn wafer; and the second case portion further including a second support portion arranged in the second recessed portion so as to support a portion of a lower surface of the sawn wafer.

13 . The case according to claim 12 , wherein the support frame is an annular ring.

14 . The case according to claim 13 , wherein the first support portions support a portion of the upper surface of the sawn wafer by pressing an upper surface of the annular ring.

15 . The case according to claim 14 , wherein the first support portions are formed so as to be contiguous with the upper surface of the annular ring and so as to press the upper surface of the annular ring from a side surface of the annular ring.

16 . The case according to claim 13 , wherein the second support portion supports the lower surface of the sawn wafer by contacting a bottom surface of the adhesive tape positioned below the annular ring.

17 . The case according to claim 13 , wherein the first case portion further includes a first ventilation route coupling a space external to the case with the first recessed portion, the first ventilation route being configured to allow the discharge of a gas from the first recessed portion into the space outside the case.

18 . The case according to claim 17 , wherein, in plan view, the first ventilation route connects a space inside the annular ring with a space outside the annular ring.

19 . The case according to claim 18 , wherein, in plan view, the first ventilation route connects the space in the first recessed portion with space outside the first support portions by penetrating through the first support portions.

20 . The case according to claim 19 , wherein a portion of the first ventilation route has a partially enlarged cross-sectional area.

21 . The case according to claim 17 , wherein the second case portion further includes a second ventilation route which couples a space outside the case with the second recessed portion, the second ventilation route being configured to allow the discharge of a gas from the second recessed portion into the space outside the case.

22 . The case according to claim 21 , wherein the first ventilation route and the second ventilation route are connected with each other.

23 . The case according to claim 21 , wherein the second ventilation route includes a gap formed between an outer edge portion of the annular ring and a wall surface of the second recessed portion.

24 . The case according to claim 12 , wherein a volume of a first space formed by the first recessed portion and the upper surface of the sawn wafer is larger than a volume of a second space formed by the second recessed portion and the lower surface of the sawn wafer.

25 . The case according to claim 12 , wherein each of the plurality of diced semiconductor chips includes an image sensor element.

26 . The case according to claim 25 , further comprising a protection tape attached onto the sawn wafer to cover the plurality of semiconductor chips.

27 . The case according to claim 12 , wherein the case is a shipping case configured to restrict movement of the sawn wafer within the case during shipment of the sawn wafer to another location.

28 . The case according to claim 27 , wherein the case is configured to be opened for removal of the sawn wafer by detaching the first case portion from the second case portion.

Assignees

• Renesas Electronics Corp

Inventors

• Matsuda Shintaro

Classifications

• H10W70/656

  Fan-in layouts · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title