Semiconductor device having error correction code (ecc) circuit

Patent metadata

Field	Value
Publication number	US-2016203045-A1
Application number	US-201514852259-A
Country	US
Kind code	A1
Filing date	Sep 11, 2015
Priority date	Jan 8, 2015
Publication date	Jul 14, 2016
Grant date	—

Abstract

An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

First claim

What is claimed is:

1 . An apparatus comprising:
n data terminals, each of the n data terminals being configured to input or output burst data of m bits, where n and m are integers more than 1; a memory cell array into which write data is written and from which read data is read, each of the write data and the read data comprising a data portion of m×n bits and a parity portion of k bits, where k is an integer more than 1; and an error correction code (ECC) control circuit configured to: receive the read data from the memory cell array to correct, if any, an error bit contained in the data portion of the read data responsive, at least in part, to the parity portion of the read data, generate a plurality of first error determination signals and a plurality of second error determination signals, each of the plurality of first error determination signals being provided in common to the n data terminals and corresponding to an associated one of the burst data of m bits, each of the plurality of second error determination signals being provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals, and detect the error bit of the data portion of the read data based, at least in part, on the first error determination signals and the second error determination signals.

2 . The apparatus of claim 1 , wherein
the ECC control circuit comprises a syndrome generator configured to generate a syndrome of j bits based on the data of m×n bits and the parity of k bits read from the memory cell array, where j is an integer more than 1; and the syndrome of j bits contains a first syndrome portion of p bits, and a second syndrome portion of q bits, where each of the p and q is an integer more than 1, wherein the first error determination signal is generated based on the first syndrome portion, and wherein the second error determination signal is generated based on the second syndrome portion.

3 . The semiconductor device according to claim 2 , further comprising a data mask terminal receiving a data mask signal of m bits corresponding to the burst data of m bits.

4 . The apparatus of claim 3 , wherein the ECC control circuit further comprises:
a first multiplexer configured to synthesize the data of m×n bits inputted into the n data terminals from outside and the data of m×n bits read from the memory cell array, of which the error bit has been corrected, based on the data mask signal; and a second multiplexer configured to synthesize the data of m×n bits inputted into the n data terminals from outside and the data of m×n bits read from the memory cell array, of which the error bit has not been corrected, based on the data mask signal.

5 . The apparatus of claim 4 , wherein the ECC control circuit comprises a write amplifier configured to write the data of m×n bits outputted from the first multiplexer into the memory cell array.

6 . The apparatus of claim 5 , wherein the ECC control circuit further comprises an encoder configured to generate the parity of k bits based on the data of m×n bits outputted from the second multiplexer.

7 . The apparatus of claim 6 , wherein the ECC control circuit further comprises a converter configured to convert based on the syndrome of q bits the parity of k bits generated by the encoder.

8 . The apparatus of claim 7 , wherein the converter is configured to be controlled based on a data position in burst data indicated by the first syndrome portion and a data position in burst data indicated by the data mask signal.

9 . The apparatus of claim 8 , wherein the converter is configured to output the parity of k bits generated by the encoder as it is when the data position in burst data indicated by the first syndrome portion and the data position in burst data indicated by the data mask signal are not coincident.

10 . The apparatus of claim 9 , wherein the converter is configured to logically synthesize the parity of k bits generated by the encoder and the syndrome of q bits when the data position in burst data indicated by the first syndrome portion and the data position in burst data indicated by the data mask signal are coincident.

11 . An apparatus comprising:
a memory cell array; a syndrome generator configured to generate a syndrome, which contains a first syndrome portion of p bits and a second syndrome portion of q bits, based on read data of m×n bits and a read parity read from the memory cell array, the read data of m×n bits being defined as m groups of n bits read data or n groups of m bits read data, where each of the m, n, p and q is an integer more than 1; and an error locator configured to specify a location of an error bit within the m groups based on the first syndrome portion, and to specify the location of the error bit within the n groups based on the second syndrome portion.

12 . The apparatus of claim 11 , wherein the error locator includes a first decoder configured to generate a first error determination signal of m bits by decoding the first syndrome portion, a second decoder configured to generate a second error determination signal of n bits by decoding the second syndrome portion, and a third decoder configured to specify the location of the error bit based on the first and second error determination signals.

13 . The apparatus of claim 12 , further comprising:
an encoder configured to generate a write parity based on write data of m×n bits; and a write amplifier configured to write the write data and the write parity into the memory cell array.

14 . The apparatus of claim 13 , further comprising a converter configured to convert a value of the write parity based on the syndrome and a data mask signal of m bits corresponding to the m bits of the write data, respectively.

15 . The semiconductor device according to claim 11 , further comprising a data mask terminal receiving a data mask signal of m bits burst data.

16 . An apparatus comprising:
a memory cell array; a plurality of data terminals into which a plurality of write data are burst-inputted; a data mask terminal configured to receive a plurality of data mask signals corresponding to the plurality of burst data, respectively; a multiplexer configured to generate data for parity generation by synthesizing the write data and a plurality of read data read from the memory cell array based on the data mask signals; an encoder configured to generate a write parity based on the data for parity generation; a syndrome generator configured to generate a syndrome based on the read data and a read parity read from the memory cell array; and a converter configured to convert a value of the write parity based on the syndrome and the data mask signal.

17 . The apparatus of claim 16 , wherein the converter is configured to be controlled based on a data position in burst data indicated by the syndrome and a data position in burst data indicated by the data mask signal.

18 . The apparatus of claim 17 , wherein when a data position in burst data indicated by the syndrome and a data position in burst data indicated by the data mask signal are not coincident, the converter is configured to directly output the write parity generated by the encoder.

19 . The apparatus of claim 18 , wherein when the data position in burst data indicated by the syndrome and the data position in burst data indicated by the data mask signal are coincident, the converter is configured to logically synthesize the write parity generated by the encoder and the syndrome.

Assignees

• Micron Technology Inc

Inventors

• Suzuki Takamasa

Classifications

• G11C29/021 Primary

  in voltage or current generators · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/0411

  Online error correction · CPC title