Memory device, memory system, and method of operating the same

Patent metadata

Field	Value
Publication number	US-9350386-B2
Application number	US-201313861676-A
Country	US
Kind code	B2
Filing date	Apr 12, 2013
Priority date	Apr 12, 2012
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a write command determination unit configured to determine whether a write command input to the memory device is accompanied by a masking signal and configured to produce a first control signal if the write command is accompanied by a masking signal, wherein the data masking signal dictates masking a portion of input write data;
a data modulation unit configured to generate modulation data in response to the first control signal by substituting the portion of input write data with a corresponding portion of read data read from the memory cell array, wherein a size of the modulation data is equal to a size of the input write data; and
an error correction code (ECC) engine configured to generate parity of the modulation data.

2. The memory device of claim 1 , wherein the write command accompanied by a masking signal is a Read Modify Write (RMW) command.

3. The memory device of claim 1 , wherein the write command determination unit determines whether an input command is a write command based on a signal applied to at least one first pin of the memory device and determines whether the write command is accompanied by a masking signal based on a signal applied to a second pin thereof.

4. The memory device of claim 3 , wherein the second pin is a command/address (CA) pin other than the at least one first pin.

5. The memory device of claim 4 , wherein the at least one first pin includes first, second and third CA pins for receiving a row address strobe signal, a write enable signal, and a column address strobe signal, respectively, and the second pin is a fourth CA pin.

6. The memory device of claim 3 , wherein the at least one first pin includes a CA pin and the second pin is a command pin.

7. The memory device of claim 1 , wherein the unit of masking, being the smallest bit-size that the data modulation unit masks the write data, has a bit-size corresponding to the bit-size of the unit of error correction by the ECC engine.

8. The memory device of claim 1 , wherein the portion of the write data and the portion of the read data respectively have a bit-size corresponding to the smallest unit of error correction by the ECC engine.

9. The memory device of claim 1 , wherein the read data was previously written to an address corresponding to the write command.

10. The memory device of claim 1 , wherein the data modulation unit comprises
a holding unit configured to receive the masking signal and to hold the masking signal until the read data is read; and
a masking unit configured to receive the masking signal from the holding unit and to replaces the portion of the write data with the corresponding portion of the read data.

11. The memory device of claim 10 , wherein the holding unit comprises a register configured to store the masking signal and a counter configured to count the number of clocks being applied to the data modulation unit.

12. The memory device of claim 1 , wherein the masking signal is input to the memory device in synchronization with transmission of the portion of the write data to be masked in the memory device.

13. The memory device of claim 1 , wherein the masking signal is input to the memory device in synchronization with transmission of the portion of the write data to be masked in the memory device, and wherein the first control signal is activated after receiving the write command and before receiving the masking signal.

14. The memory device of claim 1 , wherein the data modulation unit or the ECC engine is disposed between a data input/output (I/O) unit of the memory device, to which the write data is input, and a bank adjacent to the data I/O unit.

15. The memory device of claim 1 , wherein the memory cell array includes at least two banks, and wherein the data modulation unit is shared by at least two banks.

16. The memory device of claim 1 , wherein the memory cell array includes at least two banks, and wherein the ECC engine is shared by at least two banks.

17. The memory device of claim 1 , wherein the data modulation unit or the ECC engine is disposed at a peri region of the memory cell array.

18. The memory device of claim 1 ,
wherein the write command determination unit generates a second control signal if the write command is a normal write command, and
wherein the ECC engine generates parity of the write data in response to the second control signal.

19. A memory system including a memory device and a memory controller for applying a write command to the memory device, wherein the memory device comprises:
a memory cell array including a plurality of memory cells;
a write command determination unit configured to determine whether a write command applied to the memory device is accompanied by a masking signal and configured to produce a first control signal if the write command is accompanied by a masking signal;
a data modulation unit configured to generate modulation data in response to the first control signal by by substituting the portion of input write data with a corresponding portion of read data read from the memory cell array, wherein a size of the modulation data is equal to a size of the input write data; and
an error correction code (ECC) engine configured to generate the parity of the modulation data.

20. The system of claim 19 , wherein the write command determination unit determines whether the write command is a write command based on a signal applied to at least one first pin of the memory device and determines whether the write command is accompanied by a masking signal based on a signal applied to a second pin thereof.

21. The system of claim 20 , wherein the second pin is a command/address (CA) pin other than the at least one first pin.

22. The system of claim 19 , wherein the memory controller transmits the masking signal to the memory device in synchronization with transmission of a portion of the write data to be masked to the memory device, and wherein the data modulation unit converts the portion of the write data to be masked to a corresponding portion of the read data in response to the masking signal.

23. The system of claim 19 , wherein the first control signal is activated after receiving the write command and before receiving the masking signal.

24. A memory device comprising:
a wide input/output (I/O) interface for receiving write data and a write command;
a write command determination unit configured to determine whether the write command is a Read Modify Write (RMW) command based on a signal applied to a command/address (CA) pin in the wide I/O interface;
a data modulation unit configured to generate modulation data in response to a first control signal by substituting a portion of input write data with a corresponding portion of read data read from a memory cell array;
an error correction code (ECC) engine configured to generate parity of the modulation data; and
a writing unit which configured to write the modulation data and the parity to the memory cell array,
wherein the modulation data is formed without any part of the write command, and
wherein a size of the modulation data is equal to a sized of the input write data.

25. A mobile apparatus including a memory device, wherein the memory device comprises:
a memory cell array including a plurality of memory cells;
a write command determination unit configured to determine wheth

Assignees

• Park Jong-Wook
• Samsung Electronics Co Ltd

Inventors

• Park Jong-Wook

Classifications

• H03M13/09 Primary

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/05 Primary

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title