Peak detecting cascode for breakdown protection

Patent metadata

Field	Value
Publication number	US-2016197586-A1
Application number	US-201514978640-A
Country	US
Kind code	A1
Filing date	Dec 22, 2015
Priority date	Dec 23, 2014
Publication date	Jul 7, 2016
Grant date	—

Abstract

Peak detecting cascode for breakdown protection. In some embodiments, a power amplifier can include an amplifying transistor configured to amplify a radio-frequency (RF) signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The power amplifier can further include a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit can be configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

First claim

1 . A power amplifier (PA) comprising:
an amplifying transistor configured to amplify a radio-frequency (RF) signal; a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node; and a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit, the bias adjustment circuit configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

2 . The PA of claim 1 wherein the amplifying transistor is part of a cascode amplifier circuit.

3 . The PA of claim 2 wherein the amplifying transistor is a cascode gain stage transistor.

4 . The PA of claim 3 wherein the cascode gain stage transistor is a bipolar-junction transistor (BJT) having a base, an emitter, and a collector, such that the base is associated with the bias node and the collector is associated with the output node.

5 . The PA of claim 4 wherein the bias circuit includes an emitter follower having an emitter coupled to the base of the cascode gain stage transistor, a collector coupled to a DC voltage source, and a base coupled to a reference voltage source.

6 . The PA of claim 5 wherein the bias adjustment circuit includes a detection circuit that couples the collector of the cascode gain stage transistor and the base of the emitter follower, the detection circuit configured to be conducting when the potential difference is greater than the threshold value and non-conducting when the potential difference is less than or equal to the threshold value.

7 . The PA of claim 6 wherein the detection circuit includes one or more diodes arranged in series, the number of diodes selected based at least in part on the threshold value and turn-on characteristic of each diode.

8 . The PA of claim 7 wherein the one or more diodes include a plurality of substantially same diodes.

9 . The PA of claim 7 wherein the one or more diodes are selected to yield a potential difference threshold between the collector and base of the cascode gain stage transistor having an amount represented by V diode (N diodes +2 Vbe), V diode being a turn-on voltage of each diode, N diodes being the number of diodes, and 2 Vbe being the potential difference between the emitter of the emitter follower and the base of the cascode gain stage transistor.

10 . The PA of claim 6 wherein the bias adjustment circuit further includes a capacitance Cpk that couples the base of the emitter follower to ground, the capacitance Cpk configured to allow charge to be accumulated from the detection circuit when the detection circuit is conducting, to thereby adjust the voltage at the base of the emitter follower.

11 . The PA of claim 4 wherein the bias adjustment circuit is configured to increase the bias voltage in response to the potential difference between the collector and the base exceeding the threshold value to thereby reduce the potential difference to a value less than the threshold value.

12 . The PA of claim 11 wherein the threshold value is at or close to a breakdown voltage between the collector and the base of the BJT, such that the reduction of the potential difference prevents or reduces the likelihood of breakdown of the BJT.

13 . The PA of claim 12 wherein the bias adjustment circuit is further configured to restore the bias voltage to a normal operating value when the potential difference between the collector and the base is less than or equal to the threshold value.

14 . The PA of claim 4 wherein the cascode amplifier circuit further includes a common emitter gain stage transistor having a base configured to receive the RF signal and a collector coupled to the emitter of the cascode gain stage transistor.

15 . The PA of claim 14 wherein the common emitter gain stage transistor is configured to have a significant range of operating voltage to allow the bias voltage of the cascode gain stage transistor to be adjusted in a relatively large range to prevent or reduce the likelihood of breakdown of the cascode gain stage transistor.

16 . The PA of claim 15 wherein the relatively large range of the bias voltage available for the cascode gain stage transistor allows the cascode gain stage transistor to be operated in a normal condition with nominal voltage peaks that are near a device breakdown voltage.

17 . The PA of claim 13 wherein the bias adjustment circuit is a passive circuit having little or no impact on performance of the BJT when the bias voltage is at the normal operating value.

18 . (canceled)

19 . A semiconductor die comprising:
a semiconductor substrate; and a power amplifier (PA) implemented on the semiconductor substrate, the PA including an amplifying transistor configured to amplify a radio-frequency (RF) signal, the PA further including a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node, the PA further including a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit, the bias adjustment circuit configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.

20 . The semiconductor die of claim 19 wherein the PA is a gallium arsenide (GaAs) device.

21 . The semiconductor die of claim 19 wherein the PA is a silicon germanium (SiGe) device.

22 . (canceled)

23 . (canceled)

Assignees

• Skyworks Solutions Inc

Inventors

• Ripley David Steven

Classifications

• H04M1/0202

  Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets (constructional features of telephone transmitters or receivers, e.g. of speakers or microphones H04M1/03) · CPC title

• H03G3/3036

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H03F3/19 Primary

  with semiconductor devices only · CPC title

• H03F1/52 Primary

  Circuit arrangements for protecting such amplifiers {(monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74)} · CPC title