Amplifier Topology for Envelope Tracking

Patent metadata

Field	Value
Publication number	US-2016126901-A1
Application number	US-201414769126-A
Country	US
Kind code	A1
Filing date	Mar 20, 2014
Priority date	Mar 20, 2013
Publication date	May 5, 2016
Grant date	—

Abstract

An amplifier ( 100 ) comprises an input port ( 102 ) for receiving an input signal, an envelope port ( 104 ) for receiving an envelope signal indicative of an envelope of the input signal. The amplifier has a first transistor (M 1 ) and a second transistor (M 2 ). A first biasing circuit ( 120 ) is coupled to the envelope port ( 104 ) and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage ( 140 ) is coupled to the input port ( 102 ) for receiving the input signal, coupled to the first biasing circuit ( 120 ) for receiving the first bias voltage, coupled to a gate (g) of the first transistor (M 1 ). A second biasing circuit ( 130 ) is coupled between the envelope port ( 104 ) and a gate (g 2 ) of the second transistor (M 2 ), and is arranged to generate a second bias voltage dependent on the envelope signal.

First claim

1 . An amplifier comprising:
an input port for receiving an input signal an envelope port for receiving an envelope signal indicative of an envelope of the input signal; an output port for delivering an amplified signal; a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a source of the second transistor, and a drain of the second transistor is coupled to the output port; an inductive element coupled between the envelope port and the drain of the second transistor; a first biasing circuit coupled to the envelope port and configured to generate a first bias voltage dependent on the envelope signal; a summing stage coupled to the input port for receiving the input signal, coupled to the first biasing circuit for receiving the first bias voltage, coupled to a gate of the first transistor, and configured to deliver a sum of the input signal and the first bias voltage to the gate of the first transistor; a second biasing circuit coupled between the envelope port and a gate of the second transistor, and configured to generate a second bias voltage dependent on the envelope signal and to deliver the second bias voltage to the gate of the second transistor.

2 . The amplifier of claim 1 , wherein the first bias voltage is dependent on the envelope signal for a range of values of the envelope signal, and is independent of the envelope signal outside of the range of values of the envelope signal.

3 . The amplifier of claim 2 , wherein the range of values of the envelope signal for which the first bias voltage is dependent on the envelope signal corresponds to the envelope signal being less than a threshold, the first bias voltage being constant when the envelope signal is greater than the threshold.

4 . The amplifier of claim 1 , wherein the first and second bias voltages dependent on the envelope signal are each an affine function of the envelope signal.

5 . The amplifier of claim 1 , wherein the first bias voltage, V bias1 , dependent on the envelope signal is related to the envelope signal by V bias1 =S 1 .V env +V bias1 _ 0 , and wherein the second bias voltage, V bias2 , is related to the envelope signal by V bias2 =S 2 .V env +V bias2 _ 0 , where V env is the envelope signal, S 1 is a first constant, V bias1 _ 0 is a first quiescent voltage, S 2 is a second constant and V bias2 _ 0 is a second quiescent voltage.

6 . The amplifier of claim 5 , wherein the first biasing circuit comprises a first voltage divider configured to generate a first divided envelope signal S 1 .V env by dividing the envelope signal, and the second biasing circuit comprises a second voltage divider configured to generate a second divided envelope signal S 2 .V env by dividing the envelope signal.

7 . The amplifier of claim 6 , wherein the first voltage divider comprises a first resistive element having a variable resistance for establishing the first constant, and wherein the second voltage divider comprises a second resistive element having a variable resistance for establishing the second constant.

8 . The amplifier of claim 5 , wherein the first and second biasing circuits are configured to generate the first and second bias voltages by providing values for the first and second quiescent voltages and the first and second constants, such that, if the input signal is absent, a current drawn by the amplifier varies by less than 10% in response to a variation of the envelope signal across a maximum operating range of the amplifier.

9 . The amplifier of claim 1 , further comprising an envelope tracking stage configured to generate the envelope signal in response to the input signal.

10 . The amplifier of 9 , wherein the envelope tracking stage is configured to generate the envelope signal quantized to have fewer values than the envelope of the input signal.

11 . An electronic apparatus comprising:
an amplifier comprising:
an input port for receiving an input signal;
an envelope port for receiving an envelope signal indicative of an envelope of the input signal;
an output port for delivering an amplified signal;
a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a source of the second transistor, and a drain of the second transistor is coupled to the output port;
an inductive element coupled between the envelope port and the drain of the second transistor;
a first biasing circuit coupled to the envelope port and configured to generate a first bias voltage dependent on the envelope signal;
a summing stage coupled to the input port for receiving the input signal, coupled to the first biasing circuit for receiving the first bias voltage, coupled to a gate of the first transistor, and configured to deliver a sum of the input signal and the first bias voltage to the gate of the first transistor;
a second biasing circuit coupled between the envelope port and a gate of the second transistor, and configured to generate a second bias voltage dependent on the envelope signal and to deliver the second bias voltage to the gate of the second transistor.

12 . A method of amplification, comprising:
providing a first transistor and a second transistor, wherein a drain of the first transistor is coupled to a source of the second transistor and a drain of the second transistor is coupled to an output port; providing an inductive element coupled between an envelope port and the drain of the second transistor; receiving an input signal; receiving at the envelope port an envelope signal indicative of an envelope of the input signal; generating a first bias dependent on the envelope signal; delivering a sum of the first bias voltage and the input signal to a gate of the first transistor; generating a second bias voltage dependent on the envelope signal, and delivering the second bias voltage to a gate of the second transistor; and delivering an amplified signal at the output port.

13 . The method of amplification of claim 12 , wherein the first bias voltage is dependent on the envelope signal for a range of values of the envelope signal, and is independent of the envelope signal outside of the range of values of the envelope signal.

14 . The method of amplification of claim 13 , wherein the range of values of the envelope signal for which the first bias voltage is dependent on the envelope signal corresponds to the envelope signal being less than a threshold, and wherein the first bias voltage is constant when the envelope signal is greater than the threshold.

15 . The method of amplification of claim 12 , wherein the first bias voltage, V bias1 , dependent on the envelope signal is related to the envelope signal by V bias1 =S 1 .V env +V bias1 _ 0 , and wherein the second bias voltage, V bias2 , is related to the envelope signal by V bias2 =S 2 .V env +V bias2 _ 0 , where V env is the envelope signal, S 1 is a first constant, V bias1 _ 0 is a first quiescent voltage, S 2 is a second constant and V bias2 _ 0 is a second quiescent voltage.

Assignees

• St Ericsson Sa

Inventors

• Knopik Vincent

Classifications

• H03F1/0222 Primary

  by using a signal derived from the input signal · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/245

  with semiconductor devices only · CPC title