Thin film transistor substrate, method of manufacturing the same, and liquid crystal display panel having the same

Patent metadata

Field	Value
Publication number	US-2016133754-A1
Application number	US-201514661470-A
Country	US
Kind code	A1
Filing date	Mar 18, 2015
Priority date	Nov 6, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.

First claim

What is claimed is:

1 . A thin film transistor substrate, comprising:
a substrate; a bottom gate on the substrate; a first insulating layer on the substrate and on the bottom gate; a drain on the first insulating layer; a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain; an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source; a second insulating layer on the drain, the source, and the active layer; and a top gate on the second insulating layer.

2 . The thin film transistor as claimed in claim 1 , wherein each of the first active layer and the second active layer includes an inner channel area and an external channel area.

3 . The thin film transistor as claimed in claim 2 , wherein the inner channel area is adjacent to the first insulating layer.

4 . The thin film transistor as claimed in claim 3 , wherein the external channel area is adjacent to the second insulating layer.

5 . The thin film transistor as claimed in claim 1 , wherein the top gate includes:
a first top gate on the second insulating layer at a first side of the bottom gate; and a second top gate on the second insulating layer at a second side of the bottom gate.

6 . The thin film transistor substrate as claimed in claim 5 , wherein a same voltage is set to be applied to the bottom gate, the first top gate, and the second top gate.

7 . The thin film transistor substrate as claimed in claim 5 , wherein a same voltage is set to be applied to the first top gate and the second top gate, and a different voltage is set to be applied to the bottom gate.

8 . The thin film transistor substrate as claimed in claim 5 , wherein different voltages are set to be applied to each of the bottom gate, the first top gate, and the second top gate.

9 . The thin film transistor substrate as claimed in claim 5 , wherein the first active layer and the second active layer extend along a bent surface of the bottom gate.

10 . The thin film transistor substrate as claimed in claim 1 , wherein at least a part of the drain overlaps with the bottom gate.

11 . A method of manufacturing a thin film transistor, the method comprising:
forming a bottom gate on a substrate; forming a first insulating layer on the substrate and the bottom gate; forming a first active layer and a second active layer on a bent portion of the first insulating layer; forming a drain on the first insulating layer to contact the first active layer and the second active layer, forming a first source on the first insulating layer to contact the first active layer at a first side of the drain, and forming a second source on the first insulating layer to contact the second active layer at the other side of the drain; forming a second insulating layer on the drain, the first source, the second source, the first active layer, and the second active layer; and forming a first top gate at one side of the bottom gate on the second insulating layer and forming a second top gate at the other side of the bottom gate on the second insulating layer.

12 . The method as claimed in claim 1 , wherein each of the first active layer and the second active layer includes an inner channel area and an external channel area.

13 . The method as claimed in claim 12 , wherein the inner channel area is adjacent to the first insulating layer.

14 . The method as claimed in claim 13 , wherein the external channel area is adjacent to the second insulating layer.

15 . The method as claimed in claim 12 , wherein a same voltage is set to be applied to the bottom gate, the first top gate, and the second top gate.

16 . The method as claimed in claim 12 , wherein a same voltage is set to be applied to the first top gate and the second top gate, and a different voltage is set to be applied to the bottom gate.

17 . The method as claimed in claim 12 , wherein different voltages are set to be applied to each of the bottom gate, the first top gate, and the second top gate.

18 . The method as claimed in claim 11 , wherein forming the drain includes forming the drain to at least partially overlap the bottom gate.

19 . A liquid crystal display panel comprising:
a thin film transistor substrate including:
a bottom gate on a substrate,
a first insulating layer on the substrate and on the bottom gate,
a drain on the first insulating layer,
a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain,
an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source,
a second insulating layer on the drain, the source, and the active layer, and
a top gate on the second insulating layer;
a pixel electrode electrically connected to the drain; an opposed substrate facing the thin film transistor substrate; and a liquid crystal layer between the thin film transistor substrate and the opposed substrate.

20 . The liquid crystal display panel as claimed in claim 19 , wherein each of the first active layer and the second active layer includes an inner channel area adjacent to the first insulating layer and an external channel area adjacent to the second insulating layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Moon Yeon Keon
• Kano Masataka
• Yang Sung-Hoon
• Lim Ji Hun
• Koo So Young
• Kim Myoung Hwa
• Lim Jun Hyung

Classifications

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/031 Primary

  of thin-film transistors [TFT] · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/6733 Primary

  Multi-gate TFTs · CPC title