Localized high density substrate routing

Patent metadata

Field	Value
Publication number	US-2016197037-A1
Application number	US-201615049500-A
Country	US
Kind code	A1
Filing date	Feb 22, 2016
Priority date	Sep 28, 2012
Publication date	Jul 7, 2016
Grant date	—

Abstract

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

First claim

1 . (canceled)

2 . An interconnect element to connect between two dies, the interconnect element consisting of:
a medium including one of glass, ceramic, or silicon; first pads at least partially exposed at a first surface of the medium, the first pads to be electrically coupled to a first die; second pads at least partially exposed at the first surface of the medium; the second pads to be electrically coupled to second die; and high density routing electrically connecting respective first pads of the first pads to respective second pads of the second pads, the high density routing more dense than routing in a substrate of the first die.

3 . The interconnect element of claim 2 , wherein the high density routing is up to about 100 times more dense than routing in the substrate of the first die.

4 . The interconnect element of claim 2 , wherein the high density routing includes:
a first via electrically coupled to a pad of the first pads; a second via electrically coupled to a pad of the second pads; and a trace electrically connected to the first via and to the second via.

5 . The interconnect element of claim 2 , wherein the first pads include an exposed footprint with an area larger than a corresponding footprint of a via to connect to a pad of the first die.

6 . The interconnect element of claim 2 , wherein the medium includes silicon.

7 . The interconnect element of claim 6 , wherein the medium includes one or more layers of glass or ceramic.

8 . The interconnect element of claim 2 , wherein the medium includes a second surface opposite the first surface, wherein the second surface is an inactive surface with no electrical connectivity to the high density routing available through the second surface.

9 . An apparatus comprising:
a medium including low density interconnect routing therein; a first via; a second via; an interconnect element, the interconnect element embedded in the medium, the interconnect element including high density interconnect routing therein, the interconnect routing including a plurality of electrically conductive members, an electrically conductive member of the plurality of electrically conductive members electrically connecting the first via to the second via; a dielectric layer over the interconnect element, the dielectric layer including the first and second vias passing therethrough; and solder resist, the solder resist over the dielectric layer, the solder resist not fully covering the first and second vias.

10 . The apparatus of claim 9 , wherein the high density interconnect routing is up to about 100 times more dense than the low density interconnect routing in the medium.

11 . The apparatus of claim 9 , wherein the interconnect element includes:
a first pad at least partially exposed by a surface of the interconnect element; a third via electrically coupled to the first pad; a second pad at least partially exposed by the surface of the interconnect element; a second via electrically coupled to the second pad; and a trace electrically connected to the first via and to the second via.

12 . The apparatus of claim 9 , wherein the first pad includes an exposed footprint with an area larger than a corresponding footprint of the first via.

13 . The apparatus of claim 9 , wherein the medium includes silicon.

14 . The apparatus of claim 13 , wherein the medium includes one or more layers of glass or ceramic.

15 . The apparatus of claim 9 , wherein the medium includes a second surface opposite the first surface, wherein the second surface is an inactive surface with no electrical connectivity to the high density interconnect routing available through the second surface.

16 . A package comprising:
first and second dies; a substrate; first and second electrically conductive vias; an interconnect die, the interconnect die over the substrate, the interconnect die including an electrically conductive member embedded therein, the interconnect die including first and second electrically conductive pads, on or at least partially in, a top surface of the interconnect die, the electrically conductive member electrically connecting the first electrically conductive via to the second electrically conductive via through the first and second electrically conductive pads; an adhesive layer mechanically connecting the interconnect die to the substrate; and wherein the first die is electrically connected to the first electrically conductive via and the second die is electrically connected to the second electrically conductive via.

17 . The package of claim 16 , further comprising:
a metal pad on or at least partially in the top surface of the substrate, wherein the adhesive layer connects the interconnect die to the metal pad.

18 . The package of claim 16 , wherein a footprint of the metal pad is greater than or equal to a footprint of the interconnect die.

19 . The package of claim 16 , wherein interconnect die includes high density interconnect routing therein that is up to about 100 times more dense than the low density interconnect routing in the substrate.

20 . The package of claim 19 , wherein the interconnect die includes a bottom surface opposite the top surface, wherein the bottom surface is an inactive surface with no electrical connectivity to the high density interconnect routing available through the bottom surface.

21 . The package of claim 16 , wherein the first pad includes an exposed footprint with an area larger than a corresponding footprint of the first via.

Assignees

• Intel Corp

Inventors

• Starkston Robert
• Mallik Debendra
• Guzek John S
• Chiu Chia-Pin
• Kulkarni Deepak
• Mahajan Ravindranath V

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title