Capacitor and method for manufacturing same
US-2024347278-A1 · Oct 17, 2024 · US
US2016189864A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016189864-A1 |
| Application number | US-201615059984-A |
| Country | US |
| Kind code | A1 |
| Filing date | Mar 3, 2016 |
| Priority date | Apr 15, 2002 |
| Publication date | Jun 30, 2016 |
| Grant date | — |
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Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.
Opening claim text (preview).
1 - 50 . (canceled) 51 . A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having first, second, and additional exterior surfaces, as, and where, edges of at least some of these plates are exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the interior plates are also exposed upon at least a portion of the second surface of the capacitor, the method comprising: electrolessly plating a layer of electrically-conductive first metal directly onto the first surface including where the edges of the plates are exposed upon the first surface, the layer electrically connecting the edges of the plates where they are exposed upon the first surface; and concurrently electrolessly plating a layer of electrically-conductive first metal directly onto the second surface including where the edges of the plates are exposed upon the second surface, the layer electrically connecting the edges of the plates where they are exposed upon the second surface, wherein the layer of electrically-conductive first metal is not deposited on any of the additional surfaces which meet the first surface. 52 . The method of claim 51 , wherein electrolessly plating the layer of electrically-conductive first metal comprises: electrolessly depositing the layer of electrically-conductive first metal by immersing the entire capacitor in a plating solution. 53 . The method of claim 52 , wherein the electrically-conductive first metal layer includes at least in part copper (Cu). 54 . The method of claim 52 , wherein the electrically-conductive first metal layer includes at least in part nickel (Ni). 55 . The method of claim 52 , wherein the electrically-conductive first metal layer includes at least in part copper (Cu) in combination with nickel (Ni). 56 . The method of claim 52 further comprising: plating on top of the electrolessly-deposited electrically-conductive first-metal layer a second-metal layer of an electrically-conductive second metal. 57 . The method of claim 56 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electroless plating. 58 . The method of claim 56 , wherein the electrically-conductive second-metal layer includes at least in part nickel (Ni). 59 . The method of claim 56 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electrolytic plating. 60 . The method of claim 56 , further comprising: plating on top of the electrically-conductive second-metal layer a third-metal layer of electrically-conductive third metal. 61 . The method of claim 60 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electroless plating. 62 . The method of claim 60 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electrolytic plating. 63 . The method of claim 60 , wherein the electrically-conductive third-metal layer includes at least in part tin (Sn) in combination with lead (Pb). 64 . A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having first, second, and additional exterior surfaces, as, and where, edges of at least some of the interior plates are exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the interior plates are exposed upon at least a portion of the second surface of the capacitor, the method comprising: electrolessly plating a layer of electrically-conductive first metal directly onto the first surface including where edges of the interior plates are exposed upon the first surface by immersing the entire capacitor in a plating solution, the layer electrically connecting the interior plates at their edges where they are exposed upon the first surface; and concurrently electrolessly plating a layer of electrically-conductive first metal directly onto the second surface including where edges of the interior plates are exposed upon the second surface while the entire capacitor is immersed in the plating solution, the layer electrically connecting the interior plates at their edges where they are exposed upon the second surface, wherein the layer of electrically-conductive first metal on the second surface electrically connects along the surfaces of the capacitor to the layer of electrically-conductive first metal on the first surface. 65 . The method of claim 64 , wherein the electrically-conductive first metal includes at least in part copper (Cu). 66 . The method of claim 64 , wherein the electrically-conductive first metal layer includes at least in part nickel (Ni). 67 . The method of claim 64 , wherein the electrically-conductive first metal layer includes at least in part copper (Cu) in combination with nickel (Ni). 68 . The method of claim 64 , further comprising: plating on top of the electrolessly-deposited electrically-conductive first-metal layer a second-metal layer of an electrically-conductive second metal. 69 . The method of claim 68 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electroless plating. 70 . The method of claim 68 , wherein the electrically-conductive second-metal layer includes at least in part nickel (Ni). 71 . The method of claim 68 , wherein the plating of the second-metal layer of electrically-conductive second metal comprises: electrolytic plating. 72 . The method of claim 68 , further comprising: plating on top of the electrically-conductive second-metal layer a third-metal layer of electrically-conductive third metal. 73 . The method of claim 72 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electroless plating. 74 . The method of claim 72 , wherein the plating of the third-metal layer of electrically-conductive third metal comprises: electrolytic plating. 75 . The method of claim 72 , wherein the electrically-conductive third-metal layer includes at least in part tin (Sn) in combination with lead (Pb).
Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title
Coating with alloys · CPC title
Stacked capacitors (H01G4/33 takes precedence) · CPC title
Coating with nickel, cobalt or mixtures thereof with phosphorus or boron (C23C18/50 takes precedence) · CPC title
Electroplating characterised by the article coated · CPC title
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