Electronic packages with pre-defined via patterns and methods of making and using the same

Patent metadata

Field	Value
Publication number	US-2016183376-A1
Application number	US-201414580269-A
Country	US
Kind code	A1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.

First claim

1 . An electronic package, comprising:
a substrate; a plurality of vias defined by a corresponding plurality of pre-defined via patterns; a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias; a first conductive layer disposed on at least a portion of the metal built-up layer; and a second conductive layer disposed on the first conductive layer, wherein the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.

2 . The electronic package of claim 1 , wherein the metal built-up layer is disposed on portions of the substrate corresponding to a plurality of pre-defined trace patterns.

3 . The electronic package of claim 2 , wherein an average width of the pre-defined trace patterns is in a range from about 1 micron to about 1000 microns.

4 . The electronic package of claim 1 , wherein an average diameter of the plurality of vias is in a range from about 1 micron to about 500 microns.

5 . The electronic package of claim 1 , wherein an average pitch between two adjacently disposed vias of the plurality of vias is in a range from about 2 microns to about 1000 microns.

6 . The electronic package of claim 1 , wherein the plurality of vias comprise blind vias, through vias, or a combination thereof.

7 . The electronic package of claim 1 , wherein one or more of the metal built-up layer, the first conductive layer, and the second conductive layer comprise titanium, tantalum, copper, nickel, gold, silver, chrome, aluminum, titanium-tungsten, or combinations thereof.

8 . An electronic assembly, comprising:
an electronic package, wherein the electronic package comprises:
a substrate;
a plurality of vias defined by a corresponding plurality of pre-defined via patterns;
a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias;
a first conductive layer disposed on at least a portion of the metal built-up layer;
a second conductive layer disposed on the first conductive layer,
wherein the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer; and
an electronic device coupled to corresponding vias of the plurality of vias.

9 . The electronic assembly of claim 8 , wherein the electronic device is coupled to the pre-defined via patterns.

10 . The electronic assembly of claim 8 , wherein the plurality of vias is blind vias.

11 . The electronic assembly of claim 8 , wherein the plurality of electronic devices comprises semiconductor dies.

12 . The electronic assembly of claim 8 , wherein an average diameter of the vias of the plurality of vias is in a range from about 1 micron to about 500 microns.

13 . The electronic assembly of claim 8 , wherein an average pitch between two adjacently disposed vias of the plurality of vias is in a range from about 2 microns to about 1000 microns.

14 . A method of making an electronic package, comprising:
providing a substrate comprising a first side and a second side; disposing a metal built-up layer on the first side of the substrate to provide a plurality of pre-defined via locations and a plurality of pre-defined via patterns; coupling an electronic device to the second side of the substrate such that contact pads on the electronic device are aligned with one or more pre-defined via patterns; selectively removing portions of the substrate at the one or more pre-defined via locations of the plurality of pre-defined via locations; disposing a first conductive layer on at least a portion of the metal built-up layer; and disposing a second conductive layer on at least a portion of the first conductive layer, wherein the plurality of pre-defined via patterns corresponds to a plurality of vias that is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.

15 . The method of claim 14 , wherein the step of disposing the metal built-up layer comprises:
providing a patterned resist layer on at least a portion of the first side of the substrate; and selectively depositing metal on portions of the substrate using the patterned resist layer.

16 . The method of claim 15 , further comprising selectively removing portions of the patterned resist layer from via locations of the plurality of pre-defined via locations.

17 . The method of claim 14 , wherein the step of selectively removing the portions of the substrate comprises laser drilling the portions of the substrate.

18 . The method of claim 14 , further comprising disposing a dielectric material on at least a portion of the metal built-up layer, one or more pre-defined via locations of the plurality of pre-defined via locations, between two or more adjacently disposed pre-defined via patterns of the plurality of pre-defined via patterns, or combinations thereof.

19 . The method of claim 14 , further comprising providing a plurality of pre-defined trace patterns on the substrate.

20 . The method of claim 14 , further comprising inspecting the pre-defined via patterns and the pre-defined trace patterns prior to coupling the electronic device to the second side of the substrate.

Assignees

• Gen Electric

Inventors

• Gowda Arun Virupaksha
• Mcconnelee Paul Alan
• Tuominen Risto Ilkka

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/07323

  Active alignment, e.g. using optical alignment using marks or sensors · CPC title