Metal-insulator-metal (mim) capacitors arranged in a pattern to reduce inductance, and related methods

Patent metadata

Field	Value
Publication number	US-2016181233-A1
Application number	US-201414580900-A
Country	US
Kind code	A1
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Metal-insulator-metal (MIM) capacitors arranged in a pattern to reduce inductance, and related methods, are disclosed. In one aspect, circuits are provided that employ MIM capacitors coupled in series. The MIM capacitors are arranged in a pattern, wherein a MIM capacitor is placed so as to be electromagnetically adjacent to at least two MIM capacitors, and so that a current of the MIM capacitor flows in a direction opposite or substantially opposite of a direction in which a current of each adjacent MIM capacitor flows. The magnetic field generated at metal connections of each MIM capacitor rotates in an opposite direction of the magnetic field of each electromagnetically adjacent MIM capacitor, and thus a larger proportion of magnetic fields cancel out one another rather than combining, reducing equivalent series inductance (ESL) compared to linear arrangement of MIMs.

First claim

What is claimed is:

1 . A capacitor circuit comprising:
a plurality of metal-insulator-metal (MIM) capacitors coupled in series and arranged in a circuit in a pattern; wherein each MIM capacitor among the plurality of MIM capacitors is configured to direct current flow in a direction on an axis that is opposite or substantially opposite of a direction on the axis in which each electromagnetically adjacent MIM capacitor among the plurality of MIM capacitors is configured to direct current flow; and wherein a MIM capacitor is electromagnetically adjacent to at least two (2) MIM capacitors.

2 . The capacitor circuit of claim 1 , wherein the pattern comprises a sinusoidal-shape pattern.

3 . The capacitor circuit of claim 1 , wherein the pattern is configured to reduce inductance of the circuit.

4 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises an even number of MIM capacitors.

5 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises four (4) MIM capacitors.

6 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises six (6) MIM capacitors.

7 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises eight (8) MIM capacitors.

8 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises:
a first MIM capacitor among the plurality of MIM capacitors disposed on a substrate; a second MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the first MIM capacitor on the substrate, wherein the second MIM capacitor is serially connected to the first MIM capacitor; a third MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the second MIM capacitor on the substrate, wherein the third MIM capacitor is serially connected to the second MIM capacitor; and a fourth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the first MIM capacitor and the third MIM capacitor on the substrate, wherein the fourth MIM capacitor is serially connected to the third MIM capacitor.

9 . The capacitor circuit of claim 8 , wherein the plurality of MIM capacitors further comprises:
a fifth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the fourth MIM capacitor on the substrate, wherein the fifth MIM capacitor is serially connected to the fourth MIM capacitor; and a sixth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the third MIM capacitor and the fifth MIM capacitor on the substrate, wherein the sixth MIM capacitor is serially connected to the fifth MIM capacitor.

10 . The capacitor circuit of claim 9 , wherein the plurality of MIM capacitors further comprises:
a seventh MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the sixth MIM capacitor on the substrate, wherein the seventh MIM capacitor is serially connected to the sixth MIM capacitor; and an eighth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the fifth MIM capacitor and the seventh MIM capacitor on the substrate, wherein the eighth MIM capacitor is serially connected to the seventh MIM capacitor.

11 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises:
a first MIM capacitor among the plurality of MIM capacitors disposed on a substrate; a second MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the first MIM capacitor on the substrate, wherein the second MIM capacitor is serially connected to the first MIM capacitor; a third MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the second MIM capacitor on the substrate, wherein the third MIM capacitor is serially connected to the second MIM capacitor; a fourth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the third MIM capacitor on the substrate, wherein the fourth MIM capacitor is serially connected to the third MIM capacitor; a fifth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the second MIM capacitor and the fourth MIM capacitor on the substrate, wherein the fifth MIM capacitor is serially connected to the fourth MIM capacitor; and a sixth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the first MIM capacitor and the fifth MIM capacitor on the substrate, wherein the sixth MIM capacitor is serially connected to the fifth MIM capacitor.

12 . The capacitor circuit of claim 1 , wherein the plurality of MIM capacitors comprises:
a first MIM capacitor among the plurality of MIM capacitors disposed on a substrate; a second MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the first MIM capacitor on the substrate, wherein the second MIM capacitor is serially connected to the first MIM capacitor; a third MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the second MIM capacitor on the substrate, wherein the third MIM capacitor is serially connected to the second MIM capacitor; a fourth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the third MIM capacitor on the substrate, wherein the fourth MIM capacitor is serially connected to the third MIM capacitor; a fifth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the fourth MIM capacitor on the substrate, wherein the fifth MIM capacitor is serially connected to the fourth MIM capacitor; a sixth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the third MIM capacitor and the fifth MIM capacitor on the substrate, wherein the sixth MIM capacitor is serially connected to the fifth MIM capacitor; a seventh MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the second MIM capacitor and the sixth MIM capacitor on the substrate, wherein the seventh MIM capacitor is serially connected to the sixth MIM capacitor; and an eighth MIM capacitor among the plurality of MIM capacitors disposed electromagnetically adjacent to the first MIM capacitor and the seventh MIM capacitor on the substrate, wherein the eighth MIM capacitor is serially connected to the seventh MIM capacitor.

13 . The capacitor circuit of claim 1 , wherein each MIM capacitor among the plurality of MIM capacitors comprises a single layer MIM capacitor, comprising:
a first metal layer disposed on top of a substrate; a first dielectric layer disposed on top of the first metal layer; and a second metal layer disposed on top of the first dielectric layer.

14 . The capacitor circuit of claim 1 , wherein each MIM capacitor among the plurality of MIM capacitors comprises a vertically stacked MIM capacitor, comprising:
a first metal layer disposed on top of a substrate; a first dielectric layer disposed on top of the first metal layer; a second metal layer disposed on top of the first dielectric layer; a second dielectric layer disposed on top of the second metal layer; a third metal layer disposed on top of the second dielectric layer; and a port comprising a partition of a fourth metal layer coupled to the third metal layer.

15 . The circuit of claim 1 , wherein the plurality of MIM capacitors employs an electrical planar te

Assignees

• Qualcomm Inc

Inventors

• Yun Changhan Hobie
• Lan Je-Hsiung Jeffrey
• Kim Daeik Daniel
• Berdy David Francis
• Zuo Chengjie
• Kim Jonghae
• Mudakatte Niranjan Sunil
• Velez Mario Francisco
• Mikulka Robert Paul

Classifications

• H01G4/38

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• H01G4/33

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10D86/85 Primary

  characterised by only passive components · CPC title

• H10D84/212

  of only capacitors · CPC title