Semiconductor package assembly with through silicon via interconnect

Patent metadata

Field	Value
Publication number	US-2016181201-A1
Application number	US-201514963451-A
Country	US
Kind code	A1
Filing date	Dec 9, 2015
Priority date	Dec 23, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

First claim

What is claimed is:

1 . A semiconductor package assembly with a through silicon via (TSV) interconnect, comprising:
a first semiconductor die mounted on a base, comprising:
a semiconductor substrate;
a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region; and
a first ground TSV interconnect disposed within the interval region; and
a second semiconductor die mounted on the first semiconductor die, having a ground pad thereon, wherein the first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.

2 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the first terminal is close to a back side of the semiconductor substrate opposite to the front side.

3 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the second terminal is aligned to the front side of the semiconductor substrate.

4 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the second terminal is in connection with a first-layer metal pattern of the interconnection structure.

5 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the ground pad of the second semiconductor die corresponds to a second ground TSV interconnect of the first array of TSV interconnects or the second array of TSV interconnects of the first semiconductor die.

6 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the interval region having a width greater than a pitch of the first array of TSV interconnects and a pitch of second array of TSV interconnects.

7 . The semiconductor package assembly with a TSV interconnect as claimed in claim 5 , wherein the first semiconductor die further comprises:
a conductive layer pattern disposed on a back side of the semiconductor substrate, in connection with to the first terminal of the first ground TSV interconnect and the second ground TSV interconnect.

8 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the second terminal is coupled to the input signal ground (Vss).

9 . The semiconductor package assembly with a TSV interconnect as claimed in claim 1 , wherein the first semiconductor die further comprises:
a first array of conductive bumps and a second array of conductive bumps disposed on the first semiconductor die and in contact with the base, wherein the first array of conductive bumps corresponds to the first array of TSV interconnects, the second array of conductive bumps corresponds to the second array of TSV interconnects.

10 . The semiconductor package assembly with a TSV interconnect as claimed in claim 9 , wherein the first semiconductor die further comprises:
a first ground conductive bump disposed within the interval region on the first semiconductor die and in contact with the base, wherein the first ground

11 . A semiconductor package assembly with a through silicon via (TSV) interconnect, comprising:
a first semiconductor die mounted on a base, comprising:
a semiconductor substrate;
a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region;
a first ground TSV interconnect disposed within the interval region, coupled to an interconnection structure disposed on a front side of the semiconductor substrate; and
a conductive layer pattern disposed on a back side of the semiconductor substrate, in connection with to the first ground TSV interconnect and a second ground TSV interconnect of the first array of TSV interconnects or the second array of TSV interconnects of the first semiconductor die.

12 . The semiconductor package assembly with a TSV interconnect as claimed in claim 11 , further comprising:
a second semiconductor die mounted on the first semiconductor die, having a ground pad thereon, wherein the conductive layer pattern of the first semiconductor die is coupled to the ground pad of the second semiconductor die.

13 . The semiconductor package assembly with a TSV interconnect as claimed in claim 11 , wherein the interval region having a width greater than a pitch of the first array of TSV interconnects and a pitch of second array of TSV

14 . The semiconductor package assembly with a TSV interconnect as claimed in claim 11 , wherein the first semiconductor die further comprises:
a first array of conductive bumps and a second array of conductive bumps disposed on the first semiconductor die and in contact with the base, wherein the first array of conductive bumps corresponds to the first array of TSV interconnects, and the second array of conductive bumps corresponds to the second array of TSV interconnects.

15 . The semiconductor package assembly with a TSV interconnect as claimed in claim 14 , wherein the first semiconductor die further comprises:
a first ground conductive bump disposed within the interval region on the first semiconductor die and in contact with the base, wherein the first ground conductive bump is coupled to the first ground TSV interconnect.

16 . A semiconductor package assembly with a through silicon via (TSV) interconnect, comprising:
a first semiconductor die mounted on a base, comprising:
a semiconductor substrate;
a first array of TSV interconnects and a second array of TSV interconnects formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region; and
a first ground TSV interconnect disposed within the interval region,
wherein the first ground TSV interconnect of the first semiconductor die has a first terminal coupled to a second ground TSV interconnect of the first array of TSV interconnects or the second array of TSV interconnects of the first semiconductor die and a second terminal
wherein the first ground TSV interconnect is separated from the first array of TSV interconnects by a first distance larger than a pitch of the first array of TSV interconnects.

17 . The semiconductor package assembly with a TSV interconnect as claimed in claim 16 , wherein the first semiconductor die further comprises:
a conductive layer pattern disposed on a back side of the semiconductor substrate, in connection with to the first terminal of the first ground TSV interconnect and the second ground TSV interconnect.

18 . The semiconductor package assembly with a TSV interconnect as claimed in claim 17 , further comprising:
a second semiconductor die mounted on the first semiconductor die, having a ground pad thereon, wherein the conductive layer pattern of the first semiconductor die is coupled to the ground pad of the second semiconductor die.

19 . The semiconductor package assembly with a TSV interconnect as claimed in claim 16 , wherein the first semiconductor die further comprises:
a first array of conductive bumps and a second array of conductive bumps disposed on the first semiconductor die and in contact with the base, wherein the first array of conductive bumps corresponds to the first array of TSV interconnects, the secon

Assignees

• Mediatek Inc

Inventors

• Yang Ming-Tzong
• Hung Cheng-Chou
• Huang Wei-Che
• Huang Yu-Hua
• Lin Tzu-Hung
• Chan Kuei-Ti
• Wu Ruey-Beei
• Wu kai-bin

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/00 Primary

  Package configurations · CPC title