Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016181199-A1
Application number	US-201514848810-A
Country	US
Kind code	A1
Filing date	Sep 9, 2015
Priority date	Dec 19, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply wire, a first resistor is connected between the first pad electrode and the power-supply wire on the semiconductor chip, and a second resistor is connected between the second pad electrode and the power-supply wire on the semiconductor chip and has a resistance smaller than that of the first resistor.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an integrated circuit formed on a semiconductor chip; a first pad electrode formed on the semiconductor chip; a second pad electrode formed on the semiconductor chip; a power-supply wire formed on the semiconductor chip; a regulator that supplies a power-supply voltage to the integrated circuit via the power-supply wire; a first resistor that is connected between the first pad electrode and the power-supply wire and sets a resistance between the first pad electrode and the power-supply wire to a first resistance; and a second resistor that is connected between the second pad electrode and the power-supply wire and sets a resistance between the second pad electrode and the power-supply wire to a second resistance smaller than the first resistance.

2 . The semiconductor device according to claim 1 , comprising:
a package that seals the semiconductor chip; a first wire that is connected to the first pad electrode and is formed on the package; and a second wire that is connected to the second pad electrode and is formed on the package.

3 . The semiconductor device according to claim 2 , wherein the first pad electrode is provided in plural and is connected together via the first wire.

4 . The semiconductor device according to claim 2 ,
wherein the second pad electrode is provided in plural,
the first resistor and the second resistor are connected to the power-supply wire at different positions, and
the second pad electrodes are connected together via the second wire.

5 . The semiconductor device according to claim 2 ,
wherein the package includes: a first terminal connected to the first wire; and a second terminal connected to the second wire.

6 . The semiconductor device according to claim 5 , comprising:
a wiring substrate on which the package is implemented; and a capacitor that is implemented on the wiring substrate and is connected to the first terminal.

7 . The semiconductor device according to claim 2 , wherein the package includes a capacitor connected to the first pad electrode.

8 . The semiconductor device according to claim 1 , comprising:
a wiring substrate on which the semiconductor chip is implemented; a first wire that is connected to the first pad electrode and is formed on the wiring substrate; a second wire that is connected to the second pad electrode and is formed on the wiring substrate; and a capacitor connected to the first wire.

9 . The semiconductor device according to claim 1 ,
wherein the first resistor is a parasitic resistor of a wire connecting the first pad electrode and the power-supply wire, and the second resistor is a parasitic resistor of a wire connecting the second pad electrode and the power-supply wire.

10 . The semiconductor device according to claim 1 ,
wherein the regulator includes:
a transistor connected between a regulator power supply and the power-supply wire; and
an amplifier that controls conduction of the transistor according to output from the regulator, and
the power-supply wire is arranged in a meshed pattern on the semiconductor chip, and the transistor is distributed around the power-supply wire.

11 . A semiconductor device, comprising:
an integrated circuit formed on a semiconductor chip; a first pad electrode formed on the semiconductor chip; a second pad electrode formed on the semiconductor chip; a power-supply wire formed on the semiconductor chip; a regulator that supplies a power-supply voltage to the integrated circuit via the power-supply wire; a first wire that is connected between the first pad electrode and the power-supply wire and has a first resistance; and a second wire that is connected between the second pad electrode and the power-supply wire and has a second resistance smaller than the first resistance.

12 . The semiconductor device according to claim 11 , comprising:
a package that seals the semiconductor chip; a third wire that is connected to the first pad electrode and is formed on the package; and a fourth wire that is connected to the second pad electrode and is formed on the package.

13 . The semiconductor device according to claim 12 , wherein the first pad electrode is provided in plural and is connected together via the third wire.

14 . The semiconductor device according to claim 12 ,
wherein the second pad electrode is provided in plural,
the first wire and the second wire are connected to the power-supply wire at different positions, and
the second pad electrodes are connected together via the fourth wire.

15 . The semiconductor device according to claim 12 ,
wherein the package includes: a first terminal connected to the third wire; and a second terminal connected to the fourth wire.

16 . The semiconductor device according to claim 15 , comprising:
a wiring substrate on which the package is implemented; and a capacitor that is implemented on the wiring substrate and is connected to the first terminal.

17 . The semiconductor device according to claim 12 ,
wherein the package includes a capacitor connected to the first pad electrode.

18 . The semiconductor device according to claim 11 , comprising:
a wiring substrate on which the semiconductor chip is implemented; a third wire that is connected to the first pad electrode and is formed on the wiring substrate; a fourth wire that is connected to the second pad electrode and is formed on the wiring substrate; and a capacitor connected to the third wire in the wiring substrate.

19 . The semiconductor device according to claim 11 ,
wherein the first resistance is a resistance of a parasitic resistor of the first wire, and the second resistance is a resistance of a parasitic resistor of the second wire.

20 . The semiconductor device according to claim 11 ,
wherein the regulator includes:
a transistor connected between a regulator power supply and the power-supply wire; and
an amplifier that controls conduction of the transistor according to output from the regulator, and
the power-supply wire is arranged in a meshed pattern on the semiconductor chip, and the transistor is distributed around the power-supply wire.

Assignees

• Toshiba Kk

Inventors

• Kushibe Hidefumi
• Ideno Hiroyuki
• Usuda Masayuki

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/498 Primary

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• G05F3/02

  Regulating voltage or current · CPC title

• H01L23/5223

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic