Unipolar-switching perpendicular mram and method for using same

Patent metadata

Field	Value
Publication number	US-2016180908-A1
Application number	US-201514975419-A
Country	US
Kind code	A1
Filing date	Dec 18, 2015
Priority date	Dec 22, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

MRAM devices that are switched by unipolar electron flow are described. Embodiments use arrays of cells that include a diode or transistor with a pMTJ. The switching between the high and low resistance states of the pMTJ is achieved by electron flow in the same direction, i.e. a unipolar flow. Embodiments of the invention include methods of operating unipolar MRAM devices that include a read step after a write step to verify the operation. Embodiments also include methods of operating unipolar MRAM devices that include an iterative stepped-voltage write process that includes a plurality of write-read steps that begin with a selected voltage for the write pulse for the first iteration and gradually increase the voltage for the write pulse for the next iteration until a successful read operation occurs.

First claim

1 . An MRAM device with a memory cell that includes a Magnetic Tunnel Junction (MTJ) coupled to a selecting device, including:
said MTJ having at least one reference layer (RL) with a fixed perpendicular magnetization, at least one free layer (FL) with a switchable perpendicular magnetization, and a junction layer between the reference layer and the free layer, including: a bit line connected to an electrode of the MTJ; and a word line connected to the selecting device; and wherein a first write process switches the free layer magnetization from anti-parallel to the reference layer magnetization to parallel to the reference layer magnetization by applying a first voltage pulse having a first amplitude between the bit line and the word line; and wherein a second write process switches the free layer magnetization from parallel to the reference layer magnetization to anti-parallel to the reference layer magnetization by applying a second voltage pulse having a second amplitude between the bit line and the word line; the first and second voltage pulses inducing electrons to move from the reference layer to the free layer, and the second amplitude being higher than the first amplitude.

2 . A device according to claim 1 , wherein the selecting device is a diode that is electrically connected in series with the MTJ between the word line and the bit line.

3 . A device according to claim 1 , wherein the selecting device is a bipolar transistor that is electrically connected in series with the MTJ between the word line and the bit line, whereas said bipolar transistor having the characteristic of passing current under both positive and negative polarities with larger than three orders of magnitude when the voltage amplitude across said bipolar transistor exceeds a threshold value, than when the voltage amplitude is lower than said threshold.

4 . A device according to claim 1 , wherein the first write process uses a first write pulse with a first pulse width having said first voltage amplitude, and the second write process uses a second write pulse with a second pulse width having said second voltage amplitude.

5 . A device according to claim 4 , wherein said first pulse width is different than said second pulse width.

6 . A device according to claim 1 , wherein the second write process includes determining success or failure of the switching of the free layer magnetization to anti-parallel to the reference layer magnetization by performing a read operation.

7 . A device according to claim 6 , wherein the second write process includes increasing the second voltage amplitude and repeating the second write process if failure of the of the switching is determined.

8 . A device according to claim 1 , wherein the first write process includes determining success or failure of the switching of the free layer magnetization to parallel to the reference layer magnetization by performing a read operation.

9 . A device according to claim 8 , wherein the first write process includes increasing the first voltage amplitude and repeating the first write process if failure of the of the switching is determined.

Assignees

• Avalanche Technology Inc

Inventors

• Zhou Yuchen
• Wang Zihui
• Abedifard Ebrahim
• Huai Yiming
• Hao Xiaojie

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1677

  Verifying circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1673 Primary

  Reading or sensing circuits or methods · CPC title