Method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions in an out of order hardware software co-designed processor

Patent metadata

Field	Value
Publication number	US-2016179538-A1
Application number	US-201414576915-A
Country	US
Kind code	A1
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

First claim

What is claimed is:

1 . A processing apparatus comprising:
decode logic to decode a first instruction into a decoded first instruction, the decoded instruction including a first operand; and an execution unit to execute the decoded first instruction to access a predicate value on a predicate register stack.

2 . The apparatus as in claim 1 wherein the first instruction includes a first operand including a logical identifier of a predicate register on the predicate register stack.

3 . The apparatus as in claim 2 wherein the logical identifier of the predicate register on the predicate register stack is relative to a top of stack identifier.

4 . The apparatus as in claim 3 wherein the execution unit to read a predicate value indicated by the logical identifier and conditionally execute the decoded first instruction based on the predicate value.

5 . The apparatus as in claim 3 wherein the execution unit to read a predicate value indicated by the logical identifier and conditionally commit the decoded first instruction based on the predicate value.

6 . The apparatus as in claim 3 further comprising register rename logic to rename the logical identifier to a physical register identifier.

7 . The apparatus as in claim 6 wherein the register rename logic includes an arithmetic logical unit to compute the physical register identifier and a top of stack register to store the top of stack identifier.

8 . The apparatus as in claim 7 further comprising one or more shadow top of stack registers to store the top of stack identifier.

9 . The apparatus as in claim 1 wherein the execution unit further to generate a generated predicate value during execution of the decoded first instruction and to push the generated predicate value to the predicate register stack.

10 . The apparatus as in claim 9 wherein the execution unit further to advance a top of stack indicator after the push of the generated predicate value.

11 . A machine-readable medium having stored thereon data, which if performed by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform operations including:
decoding an instruction into a decoded first instruction; retrieving a first predicate value from a predicate register stack; and conditionally executing the decoded first instruction based on the first predicate value.

12 . The medium as in claim 11 wherein the predicate stack includes a top of stack identifier and retrieving the first predicate value from the predicate register stack includes determining a logical position in the predicate register stack based on an offset from the top of stack identifier.

13 . The medium as in claim 12 further including determining a physical register id of the logical position in the predicate register stack via predicate register rename logic.

14 . The medium as in claim 11 further comprising performing a speculative branch execution based at least in part on a second predicate value.

15 . The medium as in claim 14 further comprising reading third predicate value on the predicate register stack and aborting a speculative branch execution based on the third value.

16 . The medium as in claim 14 further comprising storing a top of stack identifier to a shadow top of stack register before performing the speculative branch execution.

17 . The medium as in claim 16 further comprising restoring the top of stack identifier for the predicate stack from a shadow top of stack register after recovering from a missed branch prediction.

18 . A processor implemented method comprising:
decoding an instruction having a first operand into a decoded first instruction; retrieving a first operand value including one or more predicate values; and pushing the one or more predicate values to a location in a predicate stack indicated by a top of stack identifier.

19 . The method as in claim 18 further comprising decoding the first operand into the one or more predicate values.

20 . The method as in claim 18 wherein the instruction is a first instruction and the top of stack identifier is advanced after pushing the one or more predicate values.

21 . The method as in claim 18 wherein the instruction is a second instruction and the top of stack identifier is not advanced after pushing the one or more predicate values to the predicate stack.

22 . The method as in claim 21 wherein the instruction is a third instruction to modify the top of stack identifier based in part on a position of the top of stack identifier before decoding the second instruction.

23 . The method as in claim 22 wherein the third instruction is to modify the top of stack identifier based on a last of the one or more predicate values pushed by the second instruction.

Assignees

• Intel Corp

Inventors

• Collins Jamison D
• Iyer Jayesh
• Winkel Sebastian
• Xekalakis Polychronis
• Chen Howard H
• Brauch Rupert

Classifications

• G06F9/30072 Primary

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30134 Primary

  Register stacks; shift registers · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/3004

  to perform operations on memory · CPC title