Instruction and logic for identifying instructions for retirement in a multi-strand out-of-order processor
US-10133582-B2 · Nov 20, 2018 · US
This page is not indexed by search engines while we improve data quality.
Iyer Jayesh patents
Iyer Jayesh is listed as an inventor on 3 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Iyer Jayesh |
| Total patents | 3 |
| First publication | Oct 20, 2016 |
| Latest publication | Nov 20, 2018 |
Notable patents
Publications ranked by popularity score, then publication date.
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3888 | 3 |
| G06F9/3851 | 3 |
| G06F9/384 | 2 |
| G06F9/30145 | 2 |
| G06F9/3869 | 2 |