Vertical trench routing in a substrate

Patent metadata

Field	Value
Publication number	US-2016174374-A1
Application number	US-201414569438-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

First claim

We claim:

1 . An electrical interconnect comprising:
a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

2 . The electrical interconnect defined in claim 1 wherein length of second portion is greater than length of the first portion.

3 . The electrical interconnect defined in claim 1 wherein the second portion extends below the first portion and the void region is above the first portion.

4 . The electrical interconnect defined in claim 3 wherein the plurality of layers includes a second ground plane layer that is below the second portion in the substrate.

5 . The electrical interconnect defined in claim 1 wherein the second portion extends above the first portion and the void region is below the first portion.

6 . The electrical interconnect defined in claim 5 wherein the plurality of layers includes a second ground plane layer that is above the second portion in the substrate.

7 . The electrical interconnect defined in claim 1 wherein:
the plurality of layers includes a second ground plane layer, the second ground plane layer being only a second partial layer and has a second void region that is closer to the pair of signal conductors than the second partial layer;
the second portion extends below the first portion and the first void region is above the first portion and each of the pair of signal conductors includes a third portion extending above the first portion; and
the first and second void regions being above and below the first portion.

8 . The electrical interconnect defined in claim 1 wherein the first and second portions of the pair of signal conductors are contained within a first dielectric layer in the plurality of layers.

9 . The electrical interconnect defined in claim 8 wherein the plurality of layers includes a second dielectric layer that abuts the first dielectric layer and the first portion of each of the plurality of signal conductors.

10 . The electrical interconnect defined in claim 1 wherein the pair of signal conductors are contained within a first dielectric layer in the plurality of layers.

11 . An electrical interconnect comprising:
a substrate having a plurality of layers including a first ground plane layer, a first dielectric layer and a second dielectric layer, a surface of the second dielectric layer abutting a surface of the first dielectric layer; a pair of signal conductors in the first dielectric layer and that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, a first side of the first portion of each of the plurality of signal conductors abutting the second dielectric layer, the second portion extending into at least one of the plurality of layers from a second side of the first portion, the second side being opposite the first side on the first portion, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

12 . The electrical interconnect defined in claim 11 wherein length of second portion is greater than length of the first portion.

13 . The electrical interconnect defined in claim 11 wherein the second portion extends below the first portion and the void region is above the first portion and the second dielectric layer.

14 . The electrical interconnect defined in claim 13 wherein the plurality of layers includes a second ground plane layer that is below the second portion in the substrate.

15 . The electrical interconnect defined in claim 11 wherein the second portion extends above the first portion and the void region is below the first portion and the second dielectric layer.

16 . The electrical interconnect defined in claim 15 wherein the plurality of layers includes a second ground plane layer that is above the second portion in the substrate.

17 . The electrical interconnect defined in claim 11 wherein:
the plurality of layers includes a second ground plane layer, the second ground plane layer being only a second partial layer and has a second void region that is closer to the pair of signal conductors than the second partial layer;
the second portion extends below the first portion and the first void region is above the first portion and each of the pair of signal conductors includes a third portion extending above the first portion; and
the first and second void regions being above and below the first portion.

18 . A method comprising:
forming a first metal routing portion on a first layer; forming a pair of signal conductors, the pair of signal conductors being a differential signal pair, each conductor of the pair of signal conductors being formed by forming a second metal routing portion that extends from the first metal routing portion into a second layer, the second layer different than the first layer, wherein width of the second metal routing portion is less than width of the first metal routing portion; and forming a first ground plane layer that comprises only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.

19 . The method defined in claim 18 wherein forming a pair of signal conductors comprises forming vertical trench routing in which a plurality of vertical trench portions protrude from first metal routing portion using a photo-resist lamination, development, etching, electroplating and stripping process.

20 . The method defined in claim 19 further comprising:
forming a second layer with vertical trench regions in a third layer;
aligning vertical trenches of the plurality of vertical trenches with vertical trench portions; and
combining the first, second and third layers.

Assignees

• Intel Corp

Inventors

• Kong Jackson
• Cheah Bok Eng
• Yong Khang Choong
• Heck Howard L
• Chen Kuan-Yu

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/095 Primary

  of vias therein · CPC title