Signal routing

Patent metadata

Field	Value
Publication number	US-2016174361-A1
Application number	US-201414567916-A
Country	US
Kind code	A1
Filing date	Dec 11, 2014
Priority date	Dec 11, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.

First claim

1 . An electronic device, comprising:
a circuit board comprising a plurality of conductive layers, the conductive layers comprising: a signal layer comprising signal traces; and a reference plane comprising an additional signal trace; wherein the additional signal trace is one of a pair of additional signal traces used for differential signaling and wherein the pair of additional signal traces have a same impedance as the signal traces in the signal layer.

2 . (canceled)

3 . (canceled)

4 . The electronic device of claim 1 , wherein a thickness of the additional signal trace is approximately 2 to 4 times the thickness of the signal traces in the signal layer.

5 . The electronic device of claim 1 , wherein a width of the additional signal trace is approximately 2 to 4 times the width of the signal traces in the signal layer.

6 . The electronic device of claim 1 , wherein a thickness of the signal trace in the signal layer is approximately 0.4 to 0.6 mils and a thickness of the additional signal traces is approximately 1.2 to 1.6 mils.

7 . The electronic device of claim 1 , wherein a width of the signal trace in the signal layer is approximately 2 to 5 mils and a width of the additional signal trace is approximately 8 to 10 mils.

8 . The electronic device of claim 1 , wherein the additional signal trace is angled relative to the signal traces in the signal layer.

9 . The electronic device of claim 1 , wherein a length of the additional signal trace is greater than approximately 7 inches and the additional signal trace is arranged to transmit a differential signal with a data rate greater than approximately 5 Gigabits per second (Gbps).

10 . The electronic device of claim 1 , wherein the additional signal trace is to transmit a 10 Gbps Universal Serial Bus (USB) signal.

11 . A multiple-layer circuit board, comprising:
a first conductive layer comprising signal traces; and a second conductive layer separated from the first conductive layer by a dielectric layer, the second conductive layer comprising a reference plane and an additional signal trace, wherein the second conductive layer is thicker than the first conductive layer; wherein the additional signal trace is one of a pair of additional signal traces used for differential signaling and wherein the pair of additional signal traces have a same impedance as the signal traces in the first conductive layer.

12 . (canceled)

13 . The multiple-layer circuit board of claim 11 , wherein a thickness of the second conductive layer is approximately 2 to 4 times the thickness of the first conductive layer and a width of the additional signal trace is approximately 2 to 4 times the width of the signal traces in the first conductive layer.

14 . The multiple-layer circuit board of claim 11 , wherein a thickness of the signal traces in the first conductive layer is approximately 0.4 to 0.6 mils and a thickness of the additional signal trace is approximately 1.2 to 1.6 mils.

15 . The multiple-layer circuit board of claim 11 , wherein a width of the signal traces in the first conductive is approximately 2 to 5 mils and a width of the additional signal trace is approximately 8 to 10 mils.

16 . The multiple-layer circuit board of claim 11 , wherein the additional signal trace is angled relative to the signal traces in the first conductive layer.

17 . The multiple-layer circuit board of claim 11 , wherein a length of the additional signal trace is greater than approximately 7 inches and the additional signal trace is to transmit a differential signal with a data rate greater than 5 Gigabits per second.

18 . The multiple-layer circuit board of claim 11 , wherein the additional signal trace is to transmit a Universal Serial Bus (USB) signal.

19 . A method of manufacturing a printed circuit board (PCB), comprising:
forming a first conductive layer comprising signal traces; forming a dielectric layer; and forming a second conductive layer comprising a reference plane and an additional signal trace that is larger than the signal traces in the first conductive layer; wherein the additional signal trace is one of a pair of additional signal traces used for differential signaling and wherein the pair of additional signal traces have approximately a same impedance as the signal traces in the first conductive layer.

20 . (canceled)

21 . The method of claim 19 , wherein a thickness of the second conductive layer is approximately 2 to 4 times the thickness of the first conductive layer and a width of the additional signal trace is approximately 2 to 4 times the width of the signal traces in the first conductive layer.

22 . The method of claim 19 , wherein a thickness of the signal traces in the first conductive layer is approximately 0.4 to 0.6 mils and a thickness of the additional signal trace is approximately 1.2 to 1.6 mils.

23 . The method of claim 19 , wherein a width of the signal traces in the first conductive layer is approximately 2 to 5 mils and a width of the additional signal traces is approximately 8 to 10 mils.

24 . The method of claim 19 , wherein forming the additional signal trace comprises forming the additional signal trace at an angle relative to the signal traces in the first conductive layer.

25 . The method of claim 19 , wherein a length of the additional signal trace is greater than approximately 7 inches and the additional signal trace is to transmit a differential signal with a data rate greater than 5 Gigabits per second.

Assignees

• Intel Corp

Inventors

• Chen Kuan-Yu
• Ling Yun
• Abdullah Mohd Muhaiyiddin Bin
• Kong Jackson Chung Peng
• Chen Chung-Hao
• Hsu Hao-Han
• Li Xiang

Classifications

• H01P3/18 Primary

  built-up from several layers to increase operating surface, i.e. alternately conductive and dielectric layers · CPC title

• H05K1/0216 Primary

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K1/0245

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title

• H01P11/003

  Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title

• H05K1/0242 Primary

  Structural details of individual signal conductors, e.g. related to the skin effect · CPC title