Apparatus and method for clock generation

Patent metadata

Field	Value
Publication number	US-2016173272-A1
Application number	US-201414568818-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

First claim

1 . An apparatus comprising:
a dithering circuit configured to repeatedly switch between a first value and a second value to generate a tuning word, wherein the dithering circuit is configured to switch at a first clock frequency from a first clock signal, wherein the first clock signal is generated from a clock and data recovery (CDR) system, wherein the tuning word comprises a multi-bit word; and an accumulator configured to add the tuning word to a previous accumulator output value to generate a new accumulator output value at a second clock frequency from a second clock signal, wherein the second clock signal is generated from a crystal oscillator.

2 . The apparatus of claim 1 , further comprising at least one logic circuit configured to generate a plurality of clock signals respectively based on a plurality of different bit values of the new accumulator output value.

3 . The apparatus of claim 1 , further comprising a resetting circuit configured to reset the accumulator based in part on the new accumulator output value.

4 . The apparatus of claim 1 , wherein the tuning word is generated based in part on an effective data rate value, and wherein the effective data rate value is generated by a processor based on the data rate of the CDR system and a scaling factor.

5 . The apparatus of claim 4 , wherein the CDR system comprises one or more data rate correcting modules configured to adjust the data rate.

6 . The apparatus of claim 2 , further comprising a transmitter module and/or a receiver module configured to receive the plurality of clock signals.

7 . The apparatus of claim 1 , wherein the new accumulator output value is further based on a programmable modulus.

8 . A method for clock generation comprising:
generating a first clock signal; receiving a second clock signal; switching repeatedly between a first value and a second value to generate a tuning word, wherein the switching occurs at a first clock frequency from the first clock signal, wherein the tuning word comprises a multi-bit word; and adding the tuning word to a previous accumulator output value to generate a new accumulator output value at a second clock frequency from the second clock signal.

9 . The method of claim 8 , further comprising generating a plurality of clock signals respectively based on a plurality of different bit values of the new accumulator output value.

10 . The method of claim 8 , further comprising resetting the accumulator based in part on the new accumulator output value.

11 . The method of claim 8 , wherein the tuning word is generated based in part on an effective data rate value, and wherein the effective data rate value is generated by a processor based on a data rate of a CDR system and a scaling factor.

12 . The method of claim 11 , further comprising adjusting the data rate with one or more data rate correcting modules.

13 . The method of claim 9 , further comprising sending the plurality of clock signals to a transmitter module and/or a receiver module.

14 . The method of claim 8 , wherein the new accumulator output value is further based on a programmable modulus.

15 . An apparatus for clock generation, the apparatus comprising:
a means for generating a first clock signal; a means for switching repeatedly between a first value and a second value to generate a tuning word, wherein the switching occurs at a first clock frequency from the first clock signal, wherein the tuning word comprises a multi-bit word; and a means for adding the tuning word to a previous accumulator output value to generate a new accumulator output value at a second clock frequency from a second clock signal.

16 . The apparatus of claim 15 , further comprising a means for generating a plurality of clock signals respectively based on a plurality of different bit values of the new accumulator output value.

17 . The apparatus of claim 15 , further comprising a means for resetting the accumulator based in part on the new accumulator output value.

18 . The apparatus of claim 15 , wherein the tuning word is generated based in part on an effective data rate value, and wherein the effective data rate value is generated by a processor based on a data rate of a CDR system and a scaling factor.

19 . The apparatus of claim 18 , further comprising a means for adjusting the data rate with one or more data rate correcting modules.

20 . The apparatus of claim 15 , wherein the new accumulator output value is further based on a programmable modulus.

Assignees

• Analog Devices Global

Inventors

• Khan Muhammad Kalimuddin
• Mulvaney Kenneth J

Classifications

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title

• H04L27/00

  Modulated-carrier systems · CPC title