Curved image sensor, method for fabricating the same, and electronic device having the same

Patent metadata

Field	Value
Publication number	US-2016172393-A1
Application number	US-201514670056-A
Country	US
Kind code	A1
Filing date	Mar 26, 2015
Priority date	Dec 15, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

A curved image sensor includes a supporting substrate, a bonding pattern provided over the supporting substrate a sensing substrate provided over the supporting substrate and in contact with the bonding pattern, and having a curved surface receiving incident light, and a fixing pattern provided over the supporting substrate and surrounding a periphery of the sensing substrate.

First claim

What is claimed is:

1 . A curved image sensor comprising:
a supporting substrate; a bonding pattern provided over the supporting substrate; a sensing substrate provided over the supporting substrate and in contact with the bonding pattern, and having a curved surface receiving incident light; and a fixing pattern provided over the supporting substrate and surrounding a periphery of the sensing substrate.

2 . The curved image sensor of claim 1 , further comprising:
a closed air cavity enclosed by the sensing substrate, the supporting substrate, and the fixing pattern, wherein the closed air cavity has a lower pressure than outside of the curved image sensor.

3 . The curved image sensor of claim 1 ,
wherein the sensing substrate includes a device wafer, and wherein the supporting substrate includes a carrier wafer.

4 . The curved image sensor of claim 1 , wherein the bonding pattern is in contact with a center of the sensing substrate.

5 . The curved image sensor of claim 1 , wherein the size of the bonding pattern is 10-20% of the size of the sensing substrate.

6 . The curved image sensor of claim 1 , wherein a width-length ratio of the bonding pattern is approximately the same as a width-length ratio of the sensing substrate.

7 . The curved image sensor of claim 1 , wherein the fixing pattern is in contact with a sidewall of the sensing substrate.

8 . The curved image sensor of claim 1 , wherein the sensing substrate has an inclined sidewall.

9 . The curved image sensor of claim 1 , wherein the fixing pattern has a donut shape.

10 . The curved image sensor of claim 1 , wherein the fixing pattern includes thermosetting material.

11 . The curved image sensor of claim 1 , further comprising:
a logic circuit layer provided over the supporting substrate and in contact with the bonding pattern and the fixing pattern; and a plurality of connectors passing through the fixing pattern and suitable for electrically connecting the sensing substrate to the logic circuit layer.

12 . A method for fabricating a curved image sensor, comprising:
providing a device wafer including a plurality of die regions and a scribe lane; forming a bonding pattern over each of the die regions; bonding a carrier wafer to the device wafer to be in contact with the bonding pattern; selectively etching the device wafer corresponding to the scribe lane to form a trench, wherein the trench separates the die regions from each other; filling the trench to form a fixing layer, wherein the fixing layer extends under the trench to form a closed air cavity enclosed by the fixing layer, the carrier wafer and each of the die regions; sawing the scribe lane to separate the die regions into a plurality of dies; and curving an upper surface of each of the dies and forming a fixing pattern supporting the curved surface.

13 . The method of claim 12 , wherein the bonding pattern is located in a center of each of the die regions.

14 . The method of claim 12 , wherein the size of the bonding pattern is 10-20% of the size of each of the die regions.

15 . The method of claim 12 , wherein a width-length ratio of the bonding pattern is approximately the same as a width-length ratio of each of die regions.

16 . The method of claim 12 , further comprising:
forming a sacrificial layer over the device wafer before the bonding of the carrier wafer to the device wafer, wherein the sacrificial layer has a surface flush with a surface of the bonding pattern; and removing the sacrificial layer before the forming of the fixing layer.

17 . The curved image sensor of claim 12 , wherein the trench has an inclined sidewall.

18 . The method of claim 12 , wherein the curving of the upper surface of each of the dies and the forming of the fixing pattern supporting the curved surface includes:
expanding air in the closed air cavity and transforming the shape of the fixing layer through a set annealing temperature, wherein the expanding and the transforming are performed simultaneously.

19 . The method of claim 18 ,
wherein the fixing layer includes an elastic polymer, and wherein the elastic polymer is a thermosetting polymer.

20 . An electronic device, comprising:
an optical system; a curved image sensor suitable for receiving light from the optical system; and a signal processing element suitable for processing a signal outputted from the curved image sensor, wherein the curved image sensor includes:
a supporting substrate;
a bonding pattern provided over the supporting substrate;
a sensing substrate provided over the supporting substrate and in contact with the bonding pattern, and having a curved surface receiving incident light; and
a fixing pattern provided over the supporting substrate and surrounding a periphery of the sensing substrate.

21 . The electronic device of claim 20 , further comprising:
a logic circuit layer provided over the supporting substrate and in contact with the bonding pattern and the fixing pattern; and a plurality of connectors passing through the fixing pattern and suitable for electrically connecting the sensing substrate to the logic circuit layer.

Assignees

• Sk Hynix Inc

Inventors

• Kim Sang-Sik

Classifications

• H10F39/80

  Constructional details of image sensors · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/12 Primary

  Image sensors · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/026

  Wafer-level processing · CPC title