Semiconductor device and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-2016172322-A1
Application number	US-201615050558-A
Country	US
Kind code	A1
Filing date	Feb 23, 2016
Priority date	Jan 28, 2013
Publication date	Jun 16, 2016
Grant date	—

Abstract

A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a wiring board including a first electrode; a semiconductor element including a second electrode; a barrier metal film provided on a surface of any one of the first electrode and the second electrode; and a connection terminal provided between the first and second electrodes, bonded to the barrier metal film, and made of solder containing tin, bismuth and zinc, wherein an alloy layer made of a material of the barrier metal film and the zinc is formed between the barrier metal film and the connection terminal.

2 . The semiconductor device according to claim 1 , wherein the barrier metal film is a metal layer containing a nickel film.

3 . The semiconductor device according to claim 2 , wherein the metal layer is a laminated film obtained by laminating the nickel film and a gold film in this order.

4 . The semiconductor device according to claim 1 , wherein major components of the solder are the tin and the bismuth.

5 . The semiconductor device according to claim 1 , wherein the concentration of the zinc in the solder is not less than 0.1 wt % and not more than 1 wt %.

Assignees

• Fujitsu Ltd

Inventors

• Shimizu Kozo
• Sakuyama Seiki
• Miyajima Toyoo

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title