Low cost low overhead serial interface for power management and other ICs

Patent metadata

Field	Value
Publication number	US-2016170930-A1
Application number	US-201414570898-A
Country	US
Kind code	A1
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Methods and apparatus relating to low cost and/or low overhead serial interface for power management and other IC (Integrated Circuit) devices are described. In an embodiment, a unique address is assigned to each of a plurality of slave devices. The plurality of slave devices are coupled in a daisy chain configuration. And, any access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access. Other embodiments are also disclosed and claimed.

First claim

1 . An apparatus comprising:
logic, at least a portion of which is in hardware, to cause assignment of a unique address to each of a plurality of slave devices, wherein the plurality of slave devices are to be coupled in a daisy chain configuration and wherein an access directed at a first slave device from the plurality of slave devices is to be allowed based at least in part on comparison of an address of the first slave device and an address associated with the access.

2 . The apparatus of claim 1 , wherein the logic is to be coupled to a first slave device of the plurality of devices via a single bidirectional communication pin.

3 . The apparatus of claim 1 , comprising logic to read back data to be stored in one of the plurality of slave devices prior to latching the data in that slave device.

4 . The apparatus of claim 1 , wherein each of the plurality of slave devices is to comprise no more than three communication pins, wherein one of the three communication pins is a bidirectional communication pin.

5 . The apparatus of claim 4 , comprising logic to cause a change in use of the bidirectional communication pin for input data or output data.

6 . The apparatus of claim 4 , wherein two of the three communication pins are unidirectional and couple the logic to each of the plurality of slave devices.

7 . The apparatus of claim 6 , wherein the two communication pins are to comprise a clock pin and a select pin.

8 . The apparatus of claim 7 , wherein each of the plurality of slave devices is to receive data in response to assertion of a signal on the select pin.

9 . The apparatus of claim 1 , comprising logic to dynamically adjust a frequency of a clock signal for each access to the plurality of the slave devices.

10 . The apparatus of claim 1 , wherein each of the plurality of the slave devices is to comprise a plurality of shift registers to store a unique address, for a corresponding slave device, and a data payload.

11 . The apparatus of claim 1 , wherein each of the plurality of the slave devices is to comprise a shift register to store a bypass bit, wherein the bypass bit is to cause the plurality of the slave devices to appear as a shift register to the logic at power on or reset of a computing system that includes the plurality of the slave devices.

12 . The apparatus of claim 1 , comprising logic to read back data to be stored in one of the plurality of slave devices prior to latching the data in that slave device on a per transaction basis.

13 . The apparatus of claim 1 , wherein the logic is to cause assignment of unique addresses to the plurality of slave devices at power on or rest of a computing system that includes the plurality of the slave devices.

14 . The apparatus of claim 1 , wherein a serial interface is to couple the plurality of slave devices in the daisy chain configuration.

15 . The apparatus of claim 1 , wherein a power management logic is to comprise the logic.

16 . The apparatus of claim 1 , wherein one of a voltage regulator, a power supply, a power management unit, or a reprogrammable power management integrated circuit is to comprise the logic.

17 . The apparatus of claim 1 , wherein a host computing system or a master device is to comprise the logic.

18 . The apparatus of claim 1 , wherein one or more of: the logic, a processor, and memory are on a single integrated circuit.

19 . A method comprising:
causing assignment of a unique address to each of a plurality of slave devices, wherein the plurality of slave devices are coupled in a daisy chain configuration and wherein an access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access.

20 . The method of claim 19 , further comprising reading back data to be stored in one of the plurality of slave devices prior to latching the data in that slave device.

21 . The method of claim 19 , further comprising causing a change in use of a bidirectional communication pin of the plurality of slave devices for input data or output data.

22 . The method of claim 19 , further comprising dynamically adjusting a frequency of a clock signal for each access to the plurality of the slave devices.

23 . A computer-readable medium comprising one or more instructions that when executed on a processor configure the processor to perform one or more operations to:
cause assignment of a unique address to each of a plurality of slave devices, wherein the plurality of slave devices are coupled in a daisy chain configuration and wherein an access directed at a first slave device from the plurality of slave devices is allowed based at least in part on comparison of an address of the first slave device and an address associated with the access.

24 . The computer-readable medium of claim 23 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to read back data to be stored in one of the plurality of slave devices prior to latching the data in that slave device.

25 . The computer-readable medium of claim 23 , further comprising one or more instructions that when executed on the processor configure the processor to perform one or more operations to cause a change in use of a bidirectional communication pin of the plurality of slave devices for input data or output data.

Assignees

• Intel Corp

Inventors

• Weng Sheldon
• Matthew George E
• Kumar Pavan
• Proefrock Wayne L
• Krishnamurthy Harish K
• Ravichandran Krishnan

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F13/404

  with address mapping · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3253

  Power saving in bus · CPC title