Response Control for Memory Modules That Include or Interface With Non-Compliant Memory Technologies

Patent metadata

Field	Value
Publication number	US-2016170831-A1
Application number	US-201314907363-A
Country	US
Kind code	A1
Filing date	Jul 25, 2013
Priority date	Jul 25, 2013
Publication date	Jun 16, 2016
Grant date	—

Abstract

Example embodiments relate to response control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller, and an interface to a non-compliant memory technology that does not comply with the data transfer standard. The memory module may include a command monitoring circuit to determine whether a command from the memory controller has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard. The memory module may include an error causing circuit that signals to the memory controller or an operating system when the command has not or will not complete within the defined amount of time.

First claim

1 . A memory module for response control, the memory module comprising:
an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller; an interface to a non-compliant memory technology that does not comply with the data transfer standard; a command monitoring circuit to analyze a command from the memory controller to the non-compliant memory technology, wherein the command monitoring circuit determines whether the command has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard; and an error causing circuit that signals to the memory controller or an operating system when the command has not or will not complete within the defined amount of time, wherein the error causing circuit uses a parity bit or error correcting code (ECC) bits of the interface to a memory bus to perform the signaling.

2 . The memory module of claim 1 , wherein the command is a read command and wherein the command monitoring circuit determines whether the non-compliant memory circuit has return data ready within the defined amount of time.

3 . The memory module of claim 1 , wherein the command is a write command and wherein the command monitoring circuit determines whether the write command will be or has been sent to the non-compliant memory circuit within the defined amount of time.

4 . The memory module of claim 1 , wherein the error causing circuit, via setting of the parity bit or ECC bits, causes the memory controller or the operating system to retry the command after a period of time.

5 . The memory module of claim 4 , further comprising a cache that stores return data for read commands that were not completed within the defined amount of time, such that the memory module can return the return data to the memory controller when the command is retried, wherein the return data can be returned within the defined amount of time after the retried command is received by the memory module.

6 . The memory module of claim 1 , wherein the data transfer standard is a double data rate (DDR) standard.

7 . The memory module of claim 6 , wherein the non-compliant memory technology is a non-volatile memory technology.

8 . The memory module of claim 1 , wherein the signaling to the memory controller or operating system is performed without using additional communication wires beyond what the memory bus uses to communicate with the memory module and the non-compliant memory technology according to the data transfer standard.

9 . A method for response control executed in a memory module, the method comprising:
receiving a command via an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller; sending the command to a non-compliant memory technology that does not comply with the data transfer standard; monitoring the command to determine whether the command has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard; and signaling an error, using a parity bit or error correcting code (ECC) bits, to the memory controller or an operating system when the command has not or will not complete within the defined amount of time, wherein the parity bit or ECC bits are part of the interface to a memory bus that complies with a data transfer standard.

10 . The method of claim 9 , wherein the parity bit or ECC bits are encoded in a manner such that the memory controller or operating system can distinguish between a real parity or ECC error and an error that indicates that a command has not or will not complete within the defined amount of time.

11 . The method of claim 9 , wherein the signaling causes the memory controller or the operating system to retry the command after a period of time.

12 . The method of claim 11 , wherein signaling the error further includes encoding the ECC bits or data bits of the interface to the memory bus with at least one of the following pieces of information:
an indication that distinguishes the error from a real parity or ECC error; an amount of time that the memory controller or operating system should wait before retrying the command; and a number of times that the memory controller or operating system should retry the command before giving up.

13 . A computing system, comprising:
a memory bus coupled to a memory controller, wherein the memory bus and memory controller comply with a double data rate (DDR) data transfer standard; a memory module that includes or interfaces with a non-compliant memory technology that does not comply with the DDR data transfer standard; and a response control circuit that is on or connected to the memory module, the response control circuit including:
an interface to the memory bus, and an interface to the non-compliant memory technology;
a command monitoring circuit to analyze a read command from the memory controller to the non-compliant memory technology, wherein the command monitoring circuit determines whether return data for the read command is ready at the non-compliant memory technology within a defined amount of time within which read commands should be completed according to the data transfer standard; and
an error causing circuit that signals to the memory controller or an operating system of the computing system when the return data is not ready within the defined amount of time, wherein the error causing circuit uses a parity bit or error correcting code (ECC) bits of the interface to a memory bus to perform the signaling.

14 . The computing system of claim 13 , wherein the error causing circuit, via setting of the parity bit or ECC bits, causes the memory controller or the operating system to retry the read command after a period of time.

15 . The computing system of claim 13 , wherein the data transfer standard is a double data rate (DDR) standard, and wherein the non-compliant memory technology is a non-volatile memory technology.

Assignees

• Hewlett Packard Development Co

Inventors

• Lesartre Gregg B
• Wheeler Andrew R
• Tillema John E
• Wade Alan Jerome

Classifications

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/064

  Management of blocks · CPC title