Finfet device including a dielectrically isolated silicon alloy fin

Patent metadata

Field	Value
Publication number	US-2016163831-A1
Application number	US-201514676909-A
Country	US
Kind code	A1
Filing date	Apr 2, 2015
Priority date	Dec 5, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.

First claim

1 . A method, comprising:
forming a fin on a semiconductor substrate; forming an isolation structure adjacent said fin; forming a silicon alloy material layer on a portion of said fin extending above said isolation structure after forming said isolation structure; and performing a thermal process to define a silicon alloy fin portion from said silicon alloy material layer and said fin and to define a first insulating layer separating said fin from said substrate.

2 . The method of claim 1 , wherein said silicon alloy material layer comprises silicon germanium.

3 . The method of claim 2 , wherein a germanium concentration of said silicon germanium is higher than a silicon concentration of said silicon germanium.

4 . The method of claim 1 , wherein said thermal process comprises a condensation process.

5 . The method of claim 1 , wherein said silicon alloy fin portion comprises a strained material.

6 . The method of claim 1 , wherein said silicon alloy fin portion has a substantially vertical sidewall profile.

7 . The method of claim 1 , wherein said silicon alloy fin portion has an oval shape.

8 . The method of claim 1 , wherein a hard mask layer is disposed on a top surface of said fin, and said forming said silicon alloy material layer comprises forming said silicon alloy material layer in the presence of said hard mask layer.

9 . The method of claim 8 , further comprising removing said hard mask layer after performing said thermal process.

10 . The method of claim 1 , further comprising forming a second insulating layer above said fin and said silicon alloy material layer prior to performing said thermal process.

11 . The method of claim 10 , further comprising recessing said second insulating layer after said thermal process to expose said silicon alloy fin portion.

12 . The method of claim 1 , wherein said performing said thermal process comprises converting a second portion of said fin not extending above said isolation structure to a dielectric material to form said first insulating layer.

13 . A method, comprising:
forming a fin on a semiconductor substrate; forming an isolation structure adjacent said fin; forming a silicon germanium material layer on a portion of said fin extending above said isolation structure after forming said isolation structure; forming a first insulating layer above said fin and said silicon germanium material; and performing a thermal condensation process to define a silicon germanium fin portion from said silicon germanium material layer and said fin and to define a second insulating layer separating said fin from said substrate.

14 . The method of claim 13 , wherein a germanium concentration of said silicon germanium is higher than a silicon concentration of said silicon germanium in said silicon germanium fin portion.

15 . The method of claim 13 , wherein said silicon germanium fin portion comprises a strained material.

16 . The method of claim 13 , wherein said silicon germanium fin portion has a substantially vertical sidewall profile.

17 . The method of claim 13 , wherein said silicon germanium fin portion has an oval shape.

18 . The method of claim 13 , wherein a hard mask layer is disposed on a top surface of said fin, and said forming said silicon germanium material layer comprises forming said silicon germanium material layer in the presence of said hard mask layer.

19 . The method of claim 13 , further comprising recessing said first insulating layer after said thermal process to expose said silicon germanium fin portion.

20 . The method of claim 13 , wherein said performing said thermal process comprises converting a second portion of said fin not extending above said isolation structure to a dielectric material to form said first insulating layer.

Assignees

• Globalfoundries Inc

Inventors

• Jacob Ajey Poovannummoottil

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/6213

  having rounded corners · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H01L21/76224

  Electricity · mapped topic