Semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016163641-A1
Application number	US-201514941702-A
Country	US
Kind code	A1
Filing date	Nov 16, 2015
Priority date	Dec 4, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer.

First claim

What is claimed is:

1 . A method for fabricating a semiconductor device, comprising:
providing a substrate having a first region and a second region; forming a first dielectric layer on a surface of the substrate; forming a second dielectric layer having a plurality of first openings exposing portion of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer in the second region and the first dielectric layer in the second region until the surface of the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer in the second region.

2 . The method according to claim 1 , the substrate further comprises:
a base substrate; an insulation layer on the base substrate; and a semiconductor layer on the insulation layer.

3 . The method according to claim 2 , wherein:
the second openings expose portions of a surface of the base substrate; and the passivation regions are formed in portions of the base substrate exposed by the second openings.

4 . The method according to claim 3 , wherein etching the second dielectric and the first dielectric layer further comprises:
etching the second dielectric layer, the first dielectric layer, the semiconductor layer, and the insulation layer to form the second openings.

5 . The method according to claim 1 , further comprising:
forming conductive vias in the first dielectric layer in the first region, wherein the first openings in the first region expose top surfaces of the conductive vias.

6 . The method according to claim 1 , before forming the second openings, further comprising:
forming a mask layer on the second dielectric layer in the first region and the first conductive layer in the first region.

7 . The method according to claim 6 , wherein:
the mask layer and the first conductive layer in the second region are used as an etching mask to etch the second dielectric layer and the first dielectric layer to form the second openings.

8 . The method according to claim 7 , wherein exposing the first dielectric layer in the first region further comprises:
removing the first conductive layer in the second region to expose the first dielectric layer in the first region.

9 . The method according to claim 6 , further comprising:
removing the first conductive layer in the second region using the mask layer as a mask to expose the first openings in the second region; forming a sacrificial layer in the first openings in the second region; and etching the second dielectric layer in the second region and the first dielectric layer in the second region using the mask layer and the sacrificial layer as an etching mask until the surface of the substrate is exposed.

10 . The method according to claim 9 , after forming the passivation regions, further comprising;
removing the sacrificial layer to expose the surface of the first dielectric layer in the first region.

11 . The method according to claim 9 , wherein:
the sacrificial layer is made of a bottom anti-reflective material.

12 . The method according to claim 1 , wherein forming the first conductive layer further comprises:
forming a first conductive film on the surface of the second dielectric layer and in the first openings; and planarizing the first conductive film until the surface of the second dielectric layer is exposed.

13 . The method according to claim 12 , wherein:
the first conductive film is formed by one of an electroplating process, a chemical plating process and a deposition process; and the first conductive film is planarized by a chemical mechanical polishing process.

14 . The method according to claim 1 , wherein forming the second conductive layer further comprises:
forming a fourth dielectric layer having a plurality of third openings on the second dielectric layer in the first region, the first conductive layer in the first region and the third dielectric layer; and forming the second conductive layer in the third openings.

15 . The method according to claim 14 , wherein:
the third openings expose the third dielectric layer in the second region and portions of the surface of the first conductive layer in the first region; a portion of the second conductive layer is on the first conductive layer in the first region; and a portion of the second conductive layer in second region is configured as the induction coil structure.

16 . A semiconductor device, comprising:
a substrate having a first region and a second region; a plurality of passivation regions blocking inducting current formed in portions of a surface of the substrate in the second region a first dielectric layer formed over the surface of the substrate; a second dielectric layer formed on a top surface of the first dielectric layer in the first region; a first conductive layer formed in the second dielectric layer and on the first dielectric layer in the first region; a third dielectric layer formed on the surface of the first dielectric layer with portions penetrating through the first dielectric layer in the second region and connecting with plurality of passivation regions; and a second conductive layer, a portion of which is configured as an inductor in the second region and a portion of which is electrically connected with the first conductive layer in the first region.

17 . The semiconductor device according to claim 16 , wherein the third dielectric layer is formed by:
etching the second dielectric layer in the second region and the first dielectric layer in the second region until the surface of the substrate is exposed to form a plurality of second openings; forming the passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; and forming the third dielectric layer on the surface of the first dielectric layer and in the second openings.

18 . The semiconductor device according to claim 16 , wherein the substrate further comprises:
a base substrate; an insulation layer on the base substrate; and a semiconductor layer on the insulation layer.

19 . The semiconductor device according to claim 16 , wherein:
the first conductive layer is made of Cu.

20 . The semiconductor device according to claim 16 , wherein:
the second conductive layer is made of Cu.

Assignees

• Semiconductor Mfg Int Shanghai

Inventors

• Bao Xiaoyan
• Ge Hongtao

Classifications

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title