Techniques for resonant rotary clocking for die-to-die communication
US-2024429865-A1 · Dec 26, 2024 · US
Parallel operation system, apparatus and medium
US2016161981A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016161981-A1 |
| Application number | US-201514956945-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 2, 2015 |
| Priority date | Dec 5, 2014 |
| Publication date | Jun 9, 2016 |
| Grant date | — |
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Abstract
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A parallel operation system includes a first node including a first processor configured to execute a first process, a second processor configured to execute a second process, and a first memory, and a second node including a third processor configured to execute a third process, a fourth processor configured to execute a fourth process, and a second memory, and a first signal line that transfers synchronization information between at least one of the first and second processors and at least one of the third and fourth processors, wherein when the first process is to be synchronized with the third process, at least one of the first and the third processors using the first signal line to execute a first synchronization process.
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What is claimed is: 1 . A parallel operation system comprising: a first node including a first processor configured to execute a first process, a second processor configured to execute a second process, and a first memory, and a second node including a third processor configured to execute a third process, a fourth processor configured to execute a fourth process, and a second memory, and a first signal line that transfers synchronization information between at…
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- What does patent US2016161981A1 cover?
- A parallel operation system includes a first node including a first processor configured to execute a first process, a second processor configured to execute a second process, and a first memory, and a second node including a third processor configured to execute a third process, a fourth processor configured to execute a fourth process, and a second memory, and a first signal line that transfe…
- Who is the assignee on this patent?
- Fujitsu Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F1/12. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jun 09 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).