Display panel and display device

Patent metadata

Field	Value
Publication number	US-2016154260-A1
Application number	US-201615016364-A
Country	US
Kind code	A1
Filing date	Feb 5, 2016
Priority date	Jan 15, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

A display panel and a display device are provided. The display panel includes a first substrate having a display region and a non-display region, a second substrate disposed opposite to the first substrate, at least a data line and at least a scan line disposed in the display region, a liquid crystal layer, a plurality of spacers and a seal disposed between the first substrate and the second substrate, a light shielding layer disposed between the first substrate and the second substrate, and including a light transmitting portion and a light shielding portion, and an alignment layer and a plurality of particles disposed on the light transmitting portion and the light shielding portion. A first surface roughness corresponding to the light transmitting portion of the non-display region is greater than a second surface roughness corresponding to the light shielding portion of the non-display region.

First claim

What is claimed is:

1 . A display panel, comprising:
a first substrate and a second substrate disposed opposite to the first substrate, wherein the first substrate has a display region and a non-display region located outside the display region; at least a data line and at least a scan line disposed in the display region; a liquid crystal layer disposed between the first substrate and the second substrate; a plurality of spacers disposed on the first substrate or on the second substrate; a seal disposed between the first substrate and the second substrate; a light shielding layer disposed on the first substrate or on the second substrate, and comprising a light transmitting portion and a light shielding portion; and an alignment layer and a plurality of particles disposed on the light transmitting portion and the light shielding portion; wherein a first surface roughness corresponding to the light transmitting portion of the non-display region is greater than a second surface roughness corresponding to the light shielding portion of the non-display region.

2 . The display panel according to claim 1 , wherein the distribution density of the particles having a size of 10-100 nm located in the non-display region is greater than the distribution density of those located in the display region.

3 . The display panel according to claim 1 , wherein the distribution density of the particles located in the non-display region having a size of 10-50 nm is greater than the distribution density of those having a size of 50-100 nm.

4 . The display panel according to claim 1 , wherein the seal has a first width and a first sidewall, the first sidewall is adjacent to the non-display region, and the distribution density of the particles located on the second substrate within a range starting from the first sidewall to less than one time the first width away from the first sidewall is different from the distribution density of those within a range starting from greater than one time the first width to less than three times the first width away from the first sidewall.

5 . The display panel according to claim 1 , wherein the first surface roughness is greater than a third surface roughness generated from the particles on the light transmitting portion of the display region of the first substrate.

6 . The display panel according to claim 1 , wherein the distribution density of the particles having a size of 50-100 nm located in the non-display region on the first substrate is lower than the distribution density of those on the second substrate.

7 . The display panel according to claim 1 , further comprising:
a plurality of thin film transistors disposed on the first substrate; a plurality of metal wires disposed on the first substrate; and a protection layer overlaying at least a portion of the metal wires, wherein the alignment layer is disposed on the protection layer for exposing a first surface of the protection layer; and the particles are disposed on at least a portion of the first surface.

8 . The display panel according to claim 7 , wherein the protection layer is in direct contact with at least one of the thin film transistors or the metal wires.

9 . The display panel according to claim 7 , wherein the protection layer comprises an inorganic dielectric material.

10 . The display panel according to claim 7 , wherein the display panel further has a plurality of nanogrooves disposed on a side of at least one of the metal wires.

11 . A display device, comprising:
a display panel, comprising:
a first substrate and a second substrate disposed opposite to the first substrate, wherein the first substrate has a display region and a non-display region located outside the display region;
at least a data line and at least a scan line disposed in the display region;
a liquid crystal layer disposed between the first substrate and the second substrate;
a plurality of spacers disposed on the first substrate or on the second substrate;
a seal disposed between the first substrate and the second substrate;
a light shielding layer disposed on the first substrate or on the second substrate, and comprising a light transmitting portion and a light shielding portion; and
an alignment layer and a plurality of particles disposed on the light transmitting portion and the light shielding portion;
wherein a first surface roughness corresponding to the light transmitting portion of the non-display region is greater than a second surface roughness corresponding to the light shielding portion of the non-display region.

12 . The display device according to claim 11 , wherein the distribution density of the particles having a size of 10-100 nm located in the non-display region is greater than the distribution density of those located in the display region.

13 . The display device according to claim 11 , wherein the distribution density of the particles located in the non-display region having a size of 10-50 nm is greater than the distribution density of those having a size of 50-100 nm.

14 . The display device according to claim 11 , wherein the seal has a first width and a first sidewall, the first sidewall is adjacent to the non-display region, and the distribution density of the particles located on the second substrate within a range starting from the first sidewall to less than one time the first width away from the first sidewall is different from the distribution density of those within a range starting from greater than one time the first width to less than three times the first width away from the first sidewall.

15 . The display device according to claim 11 , wherein the first surface roughness is greater than a third surface roughness generated from the particles on the light transmitting portion of the display region of the first substrate.

16 . The display device according to claim 11 , wherein the distribution density of the particles having a size of 50-100 nm located in the non-display region on the first substrate is lower than the distribution density of those on the second substrate.

17 . The display device according to claim 11 , further comprising:
a plurality of thin film transistors disposed on the first substrate; a plurality of metal wires disposed on the first substrate; and a protection layer overlaying at least a portion of the metal wires wherein the alignment layer is disposed on the protection layer for exposing a first surface of the protection layer; and the particles are disposed on at least a portion of the first surface.

18 . The display device according to claim 17 , wherein the protection layer is in direct contact with at least one of the thin film transistors or the metal wires.

19 . The display device according to claim 17 , wherein the protection layer comprises an inorganic dielectric material.

20 . The display device according to claim 17 , wherein the display panel further has a plurality of nanogrooves disposed on a side of at least one of the metal wires.

Assignees

• Innolux Corp

Inventors

• Chen Yu-Ju
• Huang I-Hua
• Yang Wan-Shan
• Chen Chun-Teng
• Kao Chen-Kuan
• Hsu Hsu-Kuan
• Chu Hsia-Ching
• Liu Kuei-Ling
• Chen Fu-Cheng
• Chiu Kuo-Hao
• Cheng Chu-Chun

Classifications

• G02F1/13394 Primary

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

• G02F1/133512

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

• G02F2001/133388

  Physics · mapped topic

• G02F1/1339

  Gaskets; Spacers; Sealing of cells · CPC title

• G02F1/1337 Primary

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title