Methods, apparatus and system for voltage ramp testing

Patent metadata

Field	Value
Publication number	US-2016146879-A1
Application number	US-201414553863-A
Country	US
Kind code	A1
Filing date	Nov 25, 2014
Priority date	Nov 25, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted.

First claim

What is claimed:

1 . A method, comprising:
providing a device having at least one transistor and at least one dielectric layer; providing a first voltage during a first time period for performing a stress test upon said device; providing a second voltage during a second time period for discharging at least a portion of the charge built-up as a result of said first voltage, wherein said second voltage is of an opposite polarity of said first voltage; performing a sense function during a third time period for determining a result of said stress test; and performing at least one of acquiring, storing, or transmitting data relating to a breakdown of said dielectric layer based upon said result of said stress test.

2 . The method of claim 1 , wherein performing said stress test comprises performing at least on a time dependent dielectric breakdown (TDDB) test or a bias temperature instability (BTI) test.

3 . The method of claim 1 , wherein performing a sense function during said third time period for determining said result of said stress test comprises determining at least one characteristic of said transistor.

4 . The method of claim 1 , wherein performing said stress test comprises providing a voltage ramp signal comprising:
a first stress voltage during a first stress time period; a recovery voltage during a recovery time period; a sense time period; and a second stress voltage during a second stress time, wherein said second stress voltage level is higher than the voltage level of said first stress voltage level by a ramp-step value.

5 . The method of claim 1 , wherein performing said stress test comprises providing a voltage ramp signal comprising:
a first stress voltage during a first stress time period; a first sense time period; a recovery voltage during a recovery time period; a second sense time period; and a second stress voltage during a second stress time, wherein said second stress voltage level is higher than the voltage level of said first stress voltage level by a ramp-step value.

6 . The method of claim 5 , further comprising determining at least one recoverable defect based upon a comparison between a first sense function performed during said first sense time, and a second sense function performed during said second sense time.

7 . The method of claim 1 , wherein determining a result of said stress test comprises determining at least one of a linear drain current, a saturation drain current, a linear gate threshold voltage, or a saturation gate threshold voltage of said transistor.

8 . The method of claim 1 , wherein said device is comprised of at least one of a transistor, a capacitor, a resistor, memory cell, a CMOS device, a BiCMOS device, a Flash device, a DRAM memory device, and a power device.

9 . The method of claim 1 , wherein said device is a transistor and said dielectric layer is a gate insulation layer for said transistor.

10 . The method of claim 1 , further comprising modifying at least one process parameter based said data relating to a breakdown of said dielectric layer, wherein modifying said at least one process parameter comprises modifying at least one of a temperature, a pressure, a duration, a process gas composition, a process gas concentration, and an applied voltage of a process operation.

11 . A system, comprising:
a semiconductor device processing system to provide a device comprising at least one transistor and at least one dielectric layer; a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system; and a testing module for providing a voltage ramp signal (VRS) test signal for performing a stress test to determine a breakdown of said dielectric layer and at least one characteristic of said transistor, wherein said test signal comprises:
a first stress voltage during a first stress time period;
a recovery voltage during a recovery time period;
a first sense time period; and
a second stress voltage during a second stress time, wherein said second stress voltage level is higher than the voltage level of said first stress voltage level by a ramp-step value.

12 . The system of claim 11 , further comprising a second sense time period subsequent to said recovery time period, and wherein said first sense time period is prior to said recovery time period.

13 . The system of claim 13 , wherein said processing controller is configured to modify at least one process parameter based upon based upon said data relating to a breakdown of said dielectric layer and at least one characteristic of said transistor.

14 . The system of claim 11 , further comprising:
a testing controller operatively coupled to said testing module, said testing controller configured to control an operation of said testing module; and a test data analysis unit to perform an analysis of said data relating to the breakdown of said dielectric layer and at least one characteristic of said transistor, said test data analysis unit to provide analysis data to said processing controller for modifying at least one process parameter.

15 . The system of claim 11 , wherein said stress test comprises at least one of a time dependent dielectric breakdown (TDDB) test or a bias temperature instability (BTI) test.

16 . The system of claim 15 , wherein the value of the VRS test signal during said TDDB sense period is at least one of a supply voltage level or an intended-use voltage level, and wherein said value of the test signal during said BTI sense period is the gate threshold voltage level of said transistor.

17 . The system of claim 16 , wherein said testing module comprises:
a pulse generator for generating said test signal, a measurement tool to measure; a measurement tool to measure at least one of a linear drain current, a saturation drain current, a gate threshold voltage, or a linear gate threshold voltage of said transistor; a switch to change from said stress mode to said sensor mode; and a controller to control an operation of at least one of said pulse generator, said measurement tool, and said switch.

18 . An apparatus, comprising:
a testing module for providing a voltage ramp signal (VRS) test signal for performing a stress test to determine a breakdown of a dielectric layer and at least one characteristic of a transistor, wherein said test signal comprises a plurality of pulse cycles, wherein each pulse cycle comprises:
a first stress voltage during a first stress time period;
a first sense time period for performing a first sense function;
a discharge voltage that is in an opposite polarity of said first stress voltage during a recovery time period; and
a second sense time period for performing a second sense function.

19 . The apparatus of claim 18 , wherein said first and second sense function comprises determining at least one of a linear drain current, a saturation drain current, a gate threshold voltage, or a linear gate threshold voltage of said transistor.

20 . The apparatus of claim 18 , wherein said stress test comprises at least one of a time dependent dielectric breakdown (TDDB) test or a bias temperature instability (BTI) test.

Assignees

• Global Foundries Inc
• IBM

Inventors

• Uppal Suresh
• Kerber Andreas
• Mcmahon William
• Cartier Eduard A

Classifications

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G01R31/2607

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R31/14 Primary

  Circuits therefor {, e.g. for generating test voltages, sensing circuits (G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327)} · CPC title

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title