Embedded JFETs for High Voltage Applications

Patent metadata

Field	Value
Publication number	US-2016141418-A1
Application number	US-201615004438-A
Country	US
Kind code	A1
Filing date	Jan 22, 2016
Priority date	May 25, 2012
Publication date	May 19, 2016
Grant date	—

Abstract

A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

First claim

What is claimed is:

1 . A device comprising:
a buried well region of a first conductivity type over a substrate layer; a first High Voltage Well (HVW) region of the first conductivity type over the buried well region; an insulation region over the first HVW region; a drain region of the first conductivity type on a first side of the insulation region; a gate electrode on a second side of the insulation region; a well region in a region adjacent to the insulation region, wherein the well region is of a second conductivity type opposite to the first conductivity type; a second HVW region of the first conductivity type in the well region, wherein the second HVW region overlaps a portion of the buried well region; and a source region of the first conductivity type in a top region of the second HVW region.

2 . The device of claim 1 , wherein the first conductivity type is n-type.

3 . The device of claim 1 , wherein the well region comprises a first portion and a second portion on opposite sides of the second HVW region.

4 . The device of claim 3 , wherein the well region encircles the second HVW region.

5 . The device of claim 1 , wherein the well region is configured to pinch off a current flowing through the buried well region.

6 . The device of claim 1 further comprising a buried well layer between the first HVW region and the buried well region, wherein the buried well layer is of the second conductivity type.

7 . The device of claim 1 further comprising an additional well region over the buried well region, wherein the additional well region is spaced apart from the well region by a portion of the first HVW region, and wherein the first HVW region is connected to the second HVW region to form a continuous HVW region that is connected between, and contacting, the drain region and the source region.

8 . The device of claim 1 , wherein the well region comprises strips having lengthwise directions parallel to a lengthwise direction of the second HVW region, and wherein the first HVW region is disconnected from the second HVW region.

9 . A device comprising:
a buried n-type well (BNW) region; a p-type buried layer (PBL) over and contacting the BNW region; an first high-voltage n-type well (HVNW) region comprising:
a first portion over and contacting the BNW region; and
a second portion over and contacting the PBL region;
a p-well region over and contacting the BNW region, wherein the p-well region comprises edges contacting the PBL and the first HVNW region; a second HVNW region encircled by the p-well region, with a bottom surface of the second HVW region in contact with a top surface of the BNW region; a first source region at a top surface of the second HVNW region; a drain region at a top surface of the first portion of the first HVNW region; and a first gate connected to the p-well region, wherein the first source region, the drain region, and the first gate in combination form a Junction Field-Effect Transistor (JFET).

10 . The device of claim 9 , wherein a channel region of the JFET comprises a first portion in the BNW, and a second portion in the second HVNW region.

11 . The device of claim 9 , wherein the JFET is configured so that all currents flowing between the first source region and the drain region flow under the PBL.

12 . The device of claim 9 , wherein the JFET is configured so that no current flows through the second portion of the first HVNW region.

13 . The device of claim 9 further comprising a plurality of HVNW regions encircled by the p-well region, wherein the plurality of HVNW regions and the second HVNW region are separated from each other by the p-well region, and wherein the plurality of HVNW regions forms channels of the JFET.

14 . The device of claim 9 further comprising a Metal Oxide-Semiconductor (MOS) transistor comprising:
a second source region in the p-well region, with the second source region between the first source region and the drain region; and
a second gate electrode between the second source region and the drain region, wherein the MOS transistor and the JFET share the drain region.

15 . A device comprising:
a Junction Field-Effect Transistor (JFET) comprising:
a first high-voltage n-type well region (HVNW) region;
a drain region in the first HVNW region;
an insulation region extending into the first HVNW region;
a p-well region having a sidewall connecting to a sidewall of the first HVNW region;
a second HVNW region encircled by the p-well region, with the second HVNW region forming a vertical channel of the JFET;
a first source region extending into the second HVNW region; and
a first gate connected to the p-well region.

16 . The device of claim 15 , wherein the vertical channel of the JFET further comprises a buried n-well (BNW) region under the first HVNW and the p-well region.

17 . The device of claim 16 further comprising a p-type buried layer (PBL) between the first HVNW region and the BNW region, wherein a portion of the first HVNW region has a bottom contacting a top surface of the BNW region.

18 . The device of claim 17 , wherein the PBL has an edge contacting an edge of the p-well region.

19 . The device of claim 15 further comprising a high-voltage transistor comprising:
a second gate having a portion extending directly over the insulation region; and
a second source region between the first source region and drain region.

20 . The device of claim 19 , wherein the second gate comprises an additional portion overlapping the first HVNW region and the p-well region, and the second source region extends into the p-well region.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yeh Jen-Hao
• Cheng Chih-Chang
• Su Ru-Yi
• Huo Ker Hsiao
• Chen Po-Chih
• Yang Fu-Chih
• Tsai Chun-Lin

Classifications

• H03K17/223

  in field-effect transistor switches · CPC title

• H10D64/257

  for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title