Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016141400-A1
Application number	US-201514848314-A
Country	US
Kind code	A1
Filing date	Sep 8, 2015
Priority date	Nov 13, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A semiconductor device is configured such that the distance between the trench gate in the IGBT and the trench gate in the diode is reduced or a p-well layer is provided between the trench gate in the IGBT and the trench gate in the diode.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an IGBT having a first trench gate and an emitter layer formed at a front surface side of a substrate and having a collector layer formed at a rear surface side of the substrate; and a diode having a second trench gate and an anode layer formed at the front surface side of the substrate and having a cathode layer formed at the rear surface side of the substrate, wherein the second trench gate is insulated from the first trench gate, the first trench gate has a plurality of first stripe portions and a first annular portion surrounding the diode as viewed in plan, the second trench gate has a plurality of second stripe portions and a second annular portion opposed to the first annular portion and surrounding the plurality of second stripe portions as viewed in plan, the distance between the first annular portion and the second annular portion is constant, and the distance between the first annular portion and the second annular portion is equal to or smaller than the larger one of the inter-stripe distance between the plurality of first stripe portions and the inter-stripe distance between the plurality of second stripe portions.

2 . The semiconductor device according to claim 1 , wherein the distance between the first annular portion and the second annular portion, the inter-stripe distance between the plurality of first stripe portions and the inter-stripe distance between the plurality of second stripe portions are equal to each other.

3 . A semiconductor device comprising:
an IGBT having a first trench gate and an emitter layer formed at a front surface side of a substrate and having a collector layer formed at a rear surface side of the substrate; and a diode having a second trench gate and an anode layer formed at the front surface side of the substrate and having a cathode layer formed at the rear surface side of the substrate, wherein the second trench gate is insulated from the first trench gate, the first trench gate has a plurality of first stripe portions, the second trench gate has a plurality of second stripe portions, the second trench gate is disposed in a direction of extension of the first trench gate, with gaps provided between the second trench gate and the first trench gate, and the gaps are staggered as viewed in plan.

4 . The semiconductor device according to claim 3 , wherein the length of the gaps is equal to or smaller than the larger one of the inter-stripe distance between the plurality of first stripe portions and the inter-stripe distance between the plurality of second stripe portions.

5 . The semiconductor device according to claim 3 , wherein the gaps are provided so that the shortest distance between the gaps is equal to or smaller than the larger one of the inter-stripe distance between the plurality of first stripe portions and the inter-stripe distance between the plurality of second stripe portions.

6 . A semiconductor device comprising:
an IGBT having a first trench gate and an emitter layer formed at a front surface side of a substrate having an n-type drift layer, the IGBT also having a collector layer formed at a rear surface side of the substrate; and a diode having a second trench gate and an anode layer formed at the front surface side of the substrate and having a cathode layer formed at the rear surface side of the substrate, the second trench gate being insulated from the first trench gate by being spaced apart from the first trench gate; and a p-well layer covering an end portion of the second trench gate, covering a region between end portions of the first trench gate and the second trench gate, formed deeper than the first trench gate and the second trench gate and bounded on the drift layer.

7 . The semiconductor device according to claim 6 , wherein an impurity concentration in the p-well layer is higher than an impurity concentration in a base layer of the IGBT.

8 . The semiconductor device according to claim 1 , further comprising an emitter electrode connected to the emitter layer,
wherein the second trench gate is electrically connected to the emitter electrode.

9 . The semiconductor device according to claim 1 , wherein the second trench gate is floating.

10 . The semiconductor device according to claim 1 , wherein the second trench gate is formed of a buried oxide film.

Assignees

• Mitsubishi Electric Corp

Inventors

• Takahashi Tetsuo

Classifications

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title