Method and apparatus for bit-line sensing gates on an sram cell
US-2015364183-A1 · Dec 17, 2015 · US
Multi-port memory cell
US2016141019A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016141019-A1 |
| Application number | US-201615007894-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 27, 2016 |
| Priority date | Feb 28, 2014 |
| Publication date | May 19, 2016 |
| Grant date | — |
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Abstract
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A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.
First claim
Opening claim text (preview).
What is claimed is: 1 . A circuit, comprising: a first data line; a second data line; a reference node configured to have a reference voltage level corresponding to a first logical value; and a memory cell, comprising: a data node; a first transistor and a second transistor connected in series between the first data line and the reference node, a gate of the first transistor being coupled to the data node, and the first transistor being configured to be turned off when…
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Electricity · mapped topic
- G11C11/417Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US2016141019A1 cover?
- A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the fir…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G11C11/417. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu May 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).