Efficient preemption for graphics processors

Patent metadata

Field	Value
Publication number	US-2016140686-A1
Application number	US-201414543982-A
Country	US
Kind code	A1
Filing date	Nov 18, 2014
Priority date	Nov 18, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions being inserted within a preemption window in the computer program reduces the number of live registers at each preemption instruction position. Further, the preemption instruction instructs which registers are to be saved at a particular program position, typically the registers that are live at that program position. The compiled program may be run in an execution unit. A preemption request may be made to the execution unit and executed at a next available preemption instruction in the program being run in the execution unit.

First claim

We claim:

1 . A computing system comprising:
a data interface to accept a preemption request; a compiler having a preemption instruction creator and inserter to create and insert plural preemption instructions at positions in a computer program with a reduced number of live registers within a defined preemption window; an execution unit coupled to the compiler and the data interface to execute a compiled computer program with the plural preemption instructions, the execution unit including a plurality of registers in a general purpose register or an architecture register; and memory communicating with the execution unit to store contents of live registers upon execution of the preemption request.

2 . The computing system of claim 1 , the execution unit further comprising a control flow stack.

3 . The computing system of claim 1 , further comprising an application instruction pointer associated with the execution unit.

4 . The computing system of claim 1 , further comprising a timer to communicate with the execution unit.

5 . A method of processing a preemption request comprising:
inserting one or more preemption instructions while compiling a computer program, the one or more preemption instructions being inserted within a preemption window in the computer program that reduces the number of live registers at each preemption instruction position and wherein the preemption instruction instructs which registers are to be saved at a particular program position; running the compiled program in an execution unit; making a preemption request to the execution unit; and executing the preemption request at a next available preemption instruction in the program being run in the execution unit.

6 . The method of claim 5 , further comprising:
saving register contents of the registers to be saved in a memory at the program position of the preemption instruction.

7 . The method of claim 6 , wherein the registers are registers contained in the general register files or the architecture register files.

8 . The method of claim 5 , further comprising saving the contents of a control flow stack at the position of the preemption instruction.

9 . The method of claim 5 , further comprising saving the position of an application instruction pointer at the position of execution of the preemption request.

10 . The method of claim 5 , further comprising creating a preemption window between adjacent preemption instructions, the preemption window defining a length of estimated execution time between the adjacent preemption instructions.

11 . The method of claim 5 , further comprising analyzing the computer program to determine the positions to insert the one or more preemption instructions.

12 . The method of claim 11 , wherein the analyzing determines a register pressure based on a number of live registers at various positions within the computer program.

13 . At least one computer readable storage medium comprising a set of instructions which, when executed by a computing system, cause the computing system to:
insert preemption instructions while compiling a computer program, the preemption instructions being inserted at positions in the computer program that minimize the number of registers that are live at each computer program position and wherein the preemption instruction instructs which registers are required to be saved at that program position; run the compiled program in an execution unit; and execute a preemption request at the next available preemption instruction in the program being run in the execution unit.

14 . The at least one computer readable storage medium of claim 13 , wherein the instructions, when executed, cause a computing system to:
save register contents of the registers to be saved in a memory at the program position of the preemption instruction.

15 . The at least one computer readable storage medium of claim 13 , wherein the instructions, when executed, cause a computing system to:
save the contents of a control flow stack at the position of the preemption instruction.

16 . The at least one computer readable storage medium of claim 13 , wherein the instructions, when executed, cause a computing system to:
save the position of an application instruction pointer at the position of execution of the preemption request.

17 . The at least one computer readable storage medium of claim 13 , wherein the instructions, when executed, cause a computing system to:
create a preemption window between adjacent preemption instructions, the preemption window defining a length of estimated execution time between the adjacent preemption instructions.

18 . The at least one computer readable storage medium of claim 13 , wherein the instructions, when executed, cause a computing system to:
analyze the computer program to determine the positions to insert the one or more preemption instructions.

19 . The at least one computer readable storage medium of claim 18 , wherein the instructions, when executed, cause a computing system to:
determine a register pressure based on a number of live registers at various positions within the computer program.

20 . An apparatus comprising:
a compiler having a preemption instruction creator and inserter to create and insert plural preemption instructions at positions in a computer program with a reduced number of live registers within a defined preemption window; an execution unit coupled to the compiler and the data interface to execute a compiled computer program with the plural preemption instructions, the execution unit including a plurality of registers in a general purpose register or an architecture register; and memory communicating with the execution unit to store contents of live registers upon execution of the preemption request.

21 . The apparatus of claim 20 , the execution unit further comprising a control flow stack.

22 . The apparatus of claim 20 , further comprising an application instruction pointer associated with the execution unit.

23 . The apparatus of claim 20 , further comprising a timer to communicate with the execution unit.

Assignees

• Intel Corp

Inventors

• Lueh Guei-Yuan
• Maiyuran Subramaniam
• Chen Wei-Yu
• Chen Kaiyu

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title