Testbench builder, system, device and method with phase synchronization

Patent metadata

Field	Value
Publication number	US-2016140286-A1
Application number	US-201514671983-A
Country	US
Kind code	A1
Filing date	Mar 27, 2015
Priority date	Nov 14, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT.

First claim

We claim:

1 . A method of synchronizing a plurality of simulation phases in a multi-language verification environment of a testbench for testing a device under test, the method comprising:
performing at least a first part of a first simulation phase with a first portion of the multi-language verification environment associated with a first verification protocol; posting a key to a second portion of the multi-language verification environment associated with a second verification protocol with one or more verification environment protocol interfaces after performance of the first part of the first simulation phase has begun; performing at least a second part of the first simulation phase with the second portion, wherein the second portion waits to perform the second part of the first simulation phase until the key is received; completing the first simulation phase with the second portion including posting a flag indicating completion of the first simulation phase; importing the flag to the first portion when the flag is posted with the verification environment protocol interfaces; and completing the first simulation phase and performing at least a first part of a second simulation phase with the first portion, wherein the first portion waits until the flag is received to perform the first part of the second simulation phase.

2 . The method of claim 1 , wherein the first verification protocol is implemented with system verilog.

3 . The method of claim 2 , wherein the second verification protocol is not implemented with system verilog.

4 . The method of claim 3 , wherein the multi-language verification environment protocol interfaces translate the key from the first verification protocol to the second verification protocol.

5 . The method of claim 4 , wherein the first simulation phase is divided into a pre-phase and a post-phase and the posting of the key occurs during the pre-phase as performed by the first portion and the importing of the flag occurs during the post-phase as performed by the first portion.

6 . The method of claim 5 , wherein the first portion and the second portion each comprise one or more of the group consisting of an agent, a dispatcher, a reference model and a scoreboard.

7 . The method of claim 6 , wherein the first phase comprises one or more of the group consisting of a build phase, a connect phase, a reset phase, a configure phase, a main phase, a shutdown phase, a run phase, an extract phase, a check phase, a report phase and a final phase.

8 . The method of claim 7 , wherein the performance of the first simulation phase by the first portion and the second portion overlaps in time.

9 . The method of claim 8 , wherein the key is a protected variable and the flag is a semaphore within the second verification protocol.

10 . The method of claim 9 , wherein the second verification protocol is systemC or C++.

11 . A testbench stored on a non-transitory computer readable medium for testing operation of a device under test via a plurality of simulation phases, the testbench comprising:
a multi-language verification environment having a first portion of one or more first components associated with a first verification protocol, a second portion of one or more second components associated with a second verification protocol, and one or more verification environment protocol interfaces for translating between the first verification protocol and the second verification protocol, wherein the multi-language verification environment is configured to:
performing at least a first part of a first simulation phase with the first portion;
posting a key to the second portion with the verification environment protocol interfaces after performance of the first part of the first simulation phase has begun;
performing at least a second part of the first simulation phase with the second portion, wherein the second portion waits to perform the second part of the first simulation phase until the key is received;
completing the first simulation phase with the second portion including posting a flag indicating completion of the first simulation phase;
importing the flag to the first portion when the flag is posted with the verification environment protocol interfaces; and
completing the first simulation phase and performing at least a first part of a second simulation phase with the first portion, wherein the first portion waits until the flag is received to perform the first part of the second simulation phase.

12 . The testbench of claim 11 , wherein the first verification protocol is implemented with system verilog.

13 . The testbench of claim 12 , wherein the second verification protocol is not implemented with system verilog.

14 . The testbench of claim 13 , wherein the multi-language verification environment protocol interfaces are configured to translate the key from the first verification protocol to the second verification protocol.

15 . The testbench of claim 14 , wherein the first simulation phase is divided into a pre-phase and a post-phase and the posting of the key occurs during the pre-phase as performed by the first portion and the importing of the flag occurs during the post-phase as performed by the first portion.

16 . The testbench of claim 15 , wherein the first components of the first portion and the second components of the second portion each comprise one or more of the group consisting of an agent, a dispatcher, a reference model and a scoreboard.

17 . The testbench of claim 16 , wherein the first phase comprises one or more of the group consisting of a build phase, a connect phase, a reset phase, a configure phase, a main phase, a shutdown phase, a run phase, an extract phase, a check phase, a report phase and a final phase.

18 . The testbench of claim 17 , wherein the performance of the first simulation phase by the first portion and the second portion overlaps in time.

19 . The testbench of claim 18 , wherein the key is a protected variable and the flag is a semaphore within the second verification protocol.

20 . The testbench of claim 19 , wherein the second verification protocol is systemC or C++.

21 . A testbench system stored on a non-transitory computer readable medium for performing a plurality of simulation phases, the system comprising:
a device under test; and a multi-language verification environment coupled with the device under test, wherein the multi-language verification environment has a first portion of one or more first components associated with a first verification protocol, a second portion of one or more second components associated with a second verification protocol, and one or more verification environment protocol interfaces for translating between the first verification protocol and the second verification protocol, and further wherein the multi-language verification environment is configured to:
performing at least a first part of a first simulation phase with the first portion;
posting a key to the second portion with the verification environment protocol interfaces after performance of the first part of the first simulation phase has begun;
performing at least a second part of the first simulation phase with the second portion, wherein the second portion waits to perform the second part of the first simulation phase until the key is received;
completing the first simulation phase with the second portion including posting a flag indicating completion of the first simulation phase;
importing th

Assignees

• Xpliant Inc

Inventors

• Siva Nimalan
• Han Keqin Kenneth
• Patel Saurin

Classifications

• H04L43/14

  using software, i.e. software packages (network security related monitoring H04L63/1408) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H04L43/50

  Testing arrangements · CPC title

• G06F11/261

  by simulating additional hardware, e.g. fault simulation · CPC title

• G01R31/318314

  Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261) · CPC title