Reducing register read ports for register pairs

Patent metadata

Field	Value
Publication number	US-9329868-B2
Application number	US-201414520580-A
Country	US
Kind code	B2
Filing date	Oct 22, 2014
Priority date	Jul 18, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand which spans the pair of registers. It is determined if a pairing indicator associated with the pair of registers has a first value or a second value. The first value indicates that the wide operand is stored in a wide register, and the second value indicates that the wide operand is not stored in the wide register. Based on the pairing indicator having the first value, the wide operand is read from the wide register. Based on the pairing indicator having the second value, the wide operand is read from the pair of registers. An operation is performed using the wide operand.

First claim

What is claimed is:

1. A computer program product for reducing a number of read ports for register pairs, the computer program product comprising:
a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
executing, by a computer processor, an instruction, the instruction identifying a pair of registers as containing a wide operand, the wide operand spanning the pair of registers, the executing comprising:
determining whether a value stored in a wide register corresponds to a value stored across the pair of registers;
based on determining that the value stored in the wide register corresponds to the value stored across the pair of registers, reading the wide operand from the wide register;
based on determining that the value stored in the wide register does not correspond to the value stored across the pair of registers, reading the wide operand from the pair of registers; and
performing an operation using the wide operand;
wherein only a single register read port and a single operation is required to read the wide operand when it is read from the wide register, and multiple register read ports or multiple operations are required to read the wide operand when it is read from the pair of registers.

2. The computer program product of claim 1 , wherein dataflow of execution units of the processor is as wide as the wide operand.

3. The computer program product of claim 1 , wherein the determining comprises determining whether a pairing indicator corresponding to the pair of registers has a first value or a second value, the first value indicating that the wide operand is stored in the wide register and the second value indicating that the wide operand is not stored in the wide register.

4. The computer program product of claim 3 , wherein the pairing indicator is set to the first value based on an instruction writing a wide operand across the pair of registers, wherein the wide operand is further stored in the wide register.

5. The computer program product of claim 3 , wherein the pairing indicator is set to the second value based on an instruction writing an operand to only one register of the pair of registers.

6. The computer program product of claim 1 , wherein the wide register includes one register of the pair of registers.

7. The computer program product of claim 1 , further comprising when reading a wide operand only the wide operand register needs to be obtained.

8. The computer program product of claim 3 , further including speculatively updating the pairing indicator wherein the updating comprises at least one of:
setting the pairing indicator to the first value based on an instruction storing a wide operand across paired registers;
setting the pairing indicator to the second value based on an instruction storing an operand to only one of said paired registers; and
undoing a speculative state update based on an indication of misprediction, the undoing comprising at least one of:
setting the pairing indicator to indicate that no pairings are present; and
retrieving the pairing indicator from a pairing rename register, the retrieved pairing indicator corresponding to a point prior to the point of the misprediction.

9. A method for reducing a number of read ports for register pairs, the method comprising:
executing, by a computer processor, an instruction, the instruction identifying a pair of registers as containing a wide operand, the wide operand spanning the pair of registers, the executing comprising:
determining whether a value stored in a wide register corresponds to a value stored across the pair of registers;
based on determining that the value stored in the wide register corresponds to the value stored across the pair of registers, reading the wide operand from the wide register;
based on determining that the value stored in the wide register does not correspond to the value stored across the pair of registers, reading the wide operand from the pair of registers; and
performing an operation using the wide operand;
wherein only a single register read port and a single operation is required to read the wide operand when it is read from the wide register, and multiple register read ports or multiple operations are required to read the wide operand when it is read from the pair of registers.

10. The method of claim 9 , wherein dataflow of execution units of the processor is as wide as the wide operand.

11. The method of claim 9 , wherein the determining comprises determining whether a pairing indicator corresponding to the pair of registers has a first value or a second value the first value indicating that the wide operand is stored in the wide register and the second value indicating that the wide operand is not stored in the wide register.

12. The method of claim 11 , wherein the pairing indicator is set to the first value based on an instruction writing a wide operand across the pair of registers, wherein the wide operand is further stored in the wide register.

13. The method of claim 11 , wherein the pairing indicator is set to the second value based on an instruction writing an operand to only one register of the pair of registers.

14. The method of claim 9 , wherein the wide register includes one register of the pair of registers.

15. The method of claim 9 , further comprising when reading a wide operand only the wide operand register needs to be obtained.

16. The method of claim 11 , further including speculatively updating the pairing indicator wherein the updating comprises at least one of:
setting the pairing indicator to the first value based on an instruction storing a wide operand across paired registers;
setting the pairing indicator to the second value based on an instruction storing an operand to only one of said paired registers; and
undoing a speculative state update based on an indication of misprediction, the undoing comprising at least one of:
setting the pairing indicator to indicate that no pairings are present; and
retrieving the pairing indicator from a pairing rename register, the retrieved pairing indicator corresponding to a point prior to the point of the misprediction.

Assignees

• IBM

Inventors

• Bradbury Jonathan D
• Gschwind Michael K

Classifications

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title