Performing Rounding Operations Responsive To An Instruction

Patent metadata

Field	Value
Publication number	US-2016139918-A1
Application number	US-201615003951-A
Country	US
Kind code	A1
Filing date	Jan 22, 2016
Priority date	Sep 22, 2006
Publication date	May 19, 2016
Grant date	—

Abstract

In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
a controller to receive a round instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an encoding of a round mode for the round instruction, wherein the controller is to decode the encoding; a configuration register to store a default round mode and a denormal mode; and an execution unit coupled to the controller to execute a round operation, according to the encoding of the round mode field and not according to the default round mode, responsive to the round instruction; and wherein when the denormal mode of the configuration register is set for denormal numbers as zero and the source operand is a denormal number, the processor is to convert the source operand to zero before execution of the round operation.

2 . The processor of claim 1 , wherein the round instruction is to cause a floating point value to be rounded to an integral floating point value.

3 . The processor of claim 1 , wherein the round operation is to round each of a plurality of packed floating point values in the source operand to integer valued floating point values and store each of the plurality of integer valued floating point values in the destination operand.

4 . The processor of claim 1 , wherein the controller is to determine if a precision exception is to be suppressed, based on a suppression indicator provided with the round instruction.

5 . The processor of claim 1 , wherein the execution unit comprises:
a floating point adder to receive a first operand and a second operand; and a rounder coupled to an output of the floating point adder to perform the round operation.

6 . The processor of claim 5 , wherein the controller is to provide control signals to the rounder to perform the round operation.

7 . The processor of claim 5 , wherein the floating point adder is to add a first value to the source operand if the source operand is at least equal to a threshold value, otherwise the floating point adder is to subtract the first value from the source operand.

8 . The processor of claim 1 , wherein the execution unit is to execute the round operation on at least one element of the source operand to an integer valued floating point value, wherein the source operand comprises a limited precision floating point value.

9 . The processor of claim 1 , wherein the execution unit is to execute the round operation on at least one element of the source operand to an integer value, wherein the source operand comprises a floating point value.

10 . A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
receiving a user-level rounding instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an encoding of a round mode for the user-level rounding instruction, in a control selector unit of a processor; decoding the encoding in the control selector unit; based on the decoding, determining a rounding mode for the user-level rounding instruction and dispatching the source operand and information to control the rounding mode to a floating point unit of the processor coupled to the control selector unit; and executing a rounding operation on the source operand in the floating point unit of the processor responsive to the user-level rounding instruction and according to the information, including when the source operand is a denormal number, converting the source operand to zero before executing the rounding operation.

11 . The non-transitory machine-readable medium of claim 10 , wherein the method further comprises executing the rounding operation responsive to the user-level rounding instruction and according to a rounding mode set forth in a control register of the processor based on a different encoding of the rounding mode for the user-level rounding instruction.

12 . The non-transitory machine-readable medium of claim 10 , wherein the method further comprises maintaining a value of a control register including a default rounding mode during execution of the rounding operation.

13 . The non-transitory machine-readable medium of claim 10 , wherein the method further comprises executing the rounding operation according to a round halfway away from zero mode set forth in the user-level rounding instruction.

14 . The non-transitory machine-readable medium of claim 10 , wherein the method further comprises storing a result of the rounding operation in a destination storage area corresponding to the destination operand as an integer valued floating point value, wherein the source operand comprises a limited precision floating point value.

15 . The non-transitory machine-readable medium of claim 10 , wherein the method further comprises suppressing a precision exception that results from the rounding operation based on a precision suppression indicator set forth in the user-level rounding instruction.

16 . The non-transitory machine-readable medium of claim 10 , wherein the user-level rounding instruction comprises an instruction of the instruction set architecture to perform the rounding operation on a plurality of single instruction multiple data (SIMD) elements of the source operand.

17 . A system comprising:
a processor comprising:
a controller to receive a round instruction of an instruction set architecture (ISA) having a format including a source operand, a destination operand and an encoding of a round mode for the round instruction, wherein the controller is to decode the encoding;
a configuration register to store a default round mode and a denormal mode; and
an execution unit coupled to the controller to execute a round operation, according to the encoding of the round mode field and not according to the default round mode, responsive to the round instruction; and
wherein when the denormal mode of the configuration register is set for denormal numbers as zero and the source operand is a denormal number, the processor is to convert the source operand to zero before execution of the round operation; and
a dynamic random access memory (DRAM) coupled to the processor.

18 . The system of claim 17 , wherein the execution unit comprises a floating point unit to perform the round operation on the source operand responsive to the control signals from the controller, wherein the source operand comprises a limited precision value.

19 . The system of claim 17 , wherein the execution unit is to perform the different round mode via addition of a first value to the source operand if the source operand is less than or equal to a threshold value, otherwise via addition of a second value to the source operand, wherein the first value comprises a negative floating point version of the second value.

Assignees

• Intel Corp

Inventors

• Zohar Ronen
• Story Shane

Classifications

• G06F17/10

  Complex mathematical operations {(function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544)} · CPC title

• G06F7/49947

  Rounding · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F9/30167

  of immediate specifier, e.g. constants · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title