Differential current mode low latency modulation and demodulation for chip-to-chip connection

Patent metadata

Field	Value
Publication number	US-2016134460-A1
Application number	US-201514935117-A
Country	US
Kind code	A1
Filing date	Nov 6, 2015
Priority date	May 9, 2013
Publication date	May 12, 2016
Grant date	—

Abstract

A chip-to-chip communications circuit which is particularly well-suited for short range communication (less than a few inches) from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. Differential current mode modulation in the transmitter, and demodulation in the receiver, are utilized which reduce latency and power-consumption while increasing manufacturing yields and resilience to process variations.

First claim

What is claimed is:

1 . An apparatus for performing chip-to-chip communications, comprising:
a modulation circuit and a demodulation circuit based on differential current flow, instead of absolute values of current, for communicating between a transmitting chip and a receiving chip; said modulation circuit including a digital-to-analog converter and current mode mixer for each of a plurality of data bits and one or more track pulses, each of said plurality of data bits is converted from a digital signal to an analog differential current and mixed in said current mode mixer with analog differential current outputs for other data bits during multi-frequency modulation in which the differential current is modulated in response to applying a frequency carrier at each of multiple frequencies in different current mode mixers in each modulator circuit; and said demodulation circuit including a current mode mixer and analog-to-digital converter for each of a plurality of data bits and one or more track pulses received from said modulation circuit, whereby a frequency carrier from said multiple frequencies is applied to each current mode mixer in said demodulator to demodulate the analog differential carrier prior to conversion back to a digital signal through said analog-to-digital converter.

2 . The apparatus recited in claim 1 , wherein a given number of parallel digital data bits in a first integrated circuit chip are converted to a serial current mode analog signal, configured for communication over a single I/O line by said modulator to a demodulator in a second integrated circuit chip which demodulates the analog information back into parallel digital data bits.

3 . The apparatus recited in claim 1 , wherein said multi-frequency modulation comprises quadrature amplitude modulation (QAM).

4 . The apparatus recited in claim 3 , wherein said quadrature amplitude modulation (QAM) is selected from the group of QAM orders consisting of QAM8, QAM16, QAM32, QAM64, QAM128 or QAM256.

5 . The apparatus recited in claim 1 , wherein each said current mode mixer of said modulator, and said demodulator, receives one of at least two analog signals and a modulation carrier.

6 . The apparatus recited in claim 1 , further comprising a low pass filter, applied in said demodulator after mixing is performed by said current mode mixer, to filter out adjacent frequency band signals.

7 . The apparatus recited in claim 1 , further comprising introducing hysteresis thresholding in said analog-to-digital converter within said demodulator toward avoiding incorrect signal generation.

8 . The apparatus recited in claim 7 , wherein said analog-to-digital converter incorporates comparators containing current mirrors and current mode Schmitt Triggers with adjustable hysteresis value for performing said hysteresis thresholding.

9 . The apparatus recited in claim 1 , further comprising a direct current reduction circuit within said demodulation circuit, said direct current reduction circuit configured to reduce direct current levels, and associated power consumption, prior to sending the received differential current signal to said mixer within said demodulation circuit.

10 . The apparatus recited in claim 9 , wherein said direct current reduction circuit ensures that the sum of differential current to the current mode mixer is held to a desired threshold.

11 . The apparatus recited in claim 1 , wherein said current mode mixer utilizes a mixing carrier which is a quarter duty cycle of a digital steering signal utilized in said multi-frequency modulation.

12 . The apparatus recited in claim 11 , wherein application of said quarter duty cycle signal, avoids interference between channels during multi-frequency modulation.

13 . The apparatus recited in claim 11 , further comprising a four phase mixing carrier to maintain fast current steering and avoid current starvation of current in differential transistor pairs of said current mode mixer.

14 . The apparatus recited in claim 1 , wherein said plurality of bits comprise a byte of 8 bits, or other predetermined number of bits.

15 . The apparatus recited in claim 1 , wherein said chip-to-chip communication distance is at or less than three inches.

16 . The apparatus recited in claim 1 , wherein said chip-to-chip communications apparatus benefits from reduced power consumption, shorter latency, higher tolerance to interference between neighboring through-silicon-vias and higher tolerance to fabrication process variations than existing voltage signaling regardless of whether it is in single-ended or differential mode.

17 . The apparatus recited in claim 1 , wherein said apparatus is configured for self-adjusting DC current to remove undesired differential DC current mode toward maintaining enhanced signal-to-background ratio and reduced power consumption.

18 . The apparatus recited in claim 17 , wherein said self-adjusting of DC current removes undesired DC current components induced by process variations that arise in response to chip fabrication process variations.

19 . The apparatus recited in claim 1 , wherein input impedance of a chip using said demodulator is lower when operating in said current mode compared with that of voltage mode operations, whereby a chip transmitting using said modulator is subject to lighter loading in current mode operation leading to higher speed communication under a larger capacitance loading.

20 . The apparatus recited in claim 19 , wherein said demodulator benefits from lower input impedance by using said differential current flow, which is a current mode, and is less sensitive to interference noise generated by neighboring through-silicon-vias (TSVs) which are principally operating in voltage mode, than circuits relying on voltage mode forms of communication.

21 . The apparatus recited in claim 1 , wherein said apparatus is incorporated within multi frequency band quadrature amplitude modulation (QAM) chip-to-chip transceiver circuits.

22 . The apparatus recited in claim 1 , wherein said apparatus is applicable to two-dimensional or three-dimensional chip-to-chip integrated circuit connections.

23 . The apparatus recited in claim 1 , wherein said apparatus is incorporated within an integrated circuit to allow communication between that chip and a multiplicity of other integrated circuit chips, which are located within a short distance that also incorporate the chip-to-chip communications apparatus.

24 . The apparatus recited in claim 1 , wherein said multiple frequencies comprise at least a first frequency and a second frequency.

25 . The apparatus recited in claim 1 , wherein said frequency carrier is utilized in quadrature amplitude modulation (QAM) within said modulation circuit and said demodulation circuit and comprises a 90 degree out-of-phase modulation carrier.

26 . The apparatus recited in claim 1 , wherein each said modulator circuit or demodulator circuit is configured for QAM and has two of said current mode mixers, one for encoding or decoding a Q channel, and for encoding or decoding an I channel.

27 . An apparatus for performing chip-to-chip communications, comprising:
a modulation circuit and a demodulation circuit based on differential current flow, instead of absolute values of current, for communicating between a transmitting chip and a receiving chip; said modulation circuit

Assignees

• Univ California

Inventors

• Lee Sheau Jiung
• Chang Mau-Chung Frank
• Cho Wei-Han
• Kim Yanghyo

Classifications

• H04L27/38

  Demodulator circuits; Receiver circuits · CPC title

• H04L27/362 Primary

  Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated (H04L27/366 takes precedence) · CPC title

• H04L25/0294

  Provision for current-mode coupling · CPC title

• H04L25/0282

  Provision for current-mode coupling · CPC title

• H04L5/06

  the signals being represented by different frequencies (combined with time-division multiplexing H04L5/26) · CPC title