Methods and systems for low-power and pin-efficient communications with superposition signaling codes

US9401828B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9401828-B2
Application numberUS-201113176657-A
CountryUS
Kind codeB2
Filing dateJul 5, 2011
Priority dateMay 20, 2010
Publication dateJul 26, 2016
Grant dateJul 26, 2016

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  2. Abstract

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  5. First independent claim

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Abstract

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A communication system uses a bus to transmit information, by receiving signals and mapping them to a second set of signals representing codewords of a superposition signaling code, and transmitting the second set of signals. The superposition signaling code can comprise more than one layer. The pin-efficiency can be larger than 1. The system may encode bits into a codeword of a superposition signaling code that is defined by two basis vectors of predetermined size and then have two encoders for permutation modulation codes defined by the basis vectors. The bits of information are divided into a first part representing a predetermined number of bits and a second part representing a predetermined number of bits, with the parts provided to the respective encoding circuits and their outputs combined by a superposition.

First claim

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What is claimed is: 1. A method for transmitting information over a communication bus, the method comprising: receiving a first set of signals representing the information as a plurality of bits; mapping, using an encoder, a first set of the plurality of bits to a first vector in a first set of vectors, the first set of vectors part of a first permutation modulation code, wherein the first set of the plurality of bits are mapped to the first vector according to a first set of indices, the first set of indices generated at least in part by an index generator operating on the first set of the plurality of bits; mapping using the encoder, a second set of the plurality of bits not in the first set of the plurality of bits to a second vector in a second set of vectors, the second set of vectors part of a second permutation modulation code, wherein the second set of the plurality of bits are mapped to the second vector according to a second set of indices, the second set of indices generated at least in part by the index generator operating on the second set of the plurality of bits; and providing a second set of signals for transmission over the communication bus, wherein the second set of signals is based on a vector sum of the first and second vectors, wherein the vector sum forms a codeword of a superposition signaling code that is based on the first and second sets of vectors, and wherein each signal of the second set is transmitted over a respective wire of the bus. 2. The method of claim 1 , wherein a pin-efficiency is larger than 1. 3. The method of claim 1 , wherein a pin-efficiency is larger than 1.5. 4. The method of claim 1 , wherein the index generator generates the first and second sets of indices corresponding to a permutation of a basis vector. 5. The method of claim 1 , wherein the mapping includes combining a plurality of secondary codewords to form the codeword of the superposition signaling code, wherein the plurality of secondary codewords are combined as voltages. 6. The method of claim 1 , wherein the vector sum is formed by combining currents associated with the first and second vectors. 7. The method of claim 1 , wherein the vector sum is formed by wiring connections associated with the first and second vectors. 8. The method of claim 1 , wherein a number of components of the first vector is equal to a number of components of the second vector. 9. The method of claim 1 , wherein a number of components of the first vector is not equal to a number of components of the second vector. 10. The method of claim 1 , further comprising: mapping, using the encoder, a third set of the plurality of bits not in the first or second set to a third vector in a third set of vectors, the third set of vectors selected from a third permutation modulation code, wherein the second set of signals is based on a vector sum of the first, second, and third vectors. 11. A method for encoding a predetermined number, k, of bits of information into a codeword of a superposition signaling code that is defined by a first basis vector of predetermined size, n 1 , and a second basis vector of predetermined size, n 2 , the method comprising: providing a first encoder for a permutation modulation code defined by the first basis vector, the first encoder including a first index generator; providing a second encoder for a permutation modulation code defined by the second basis vector, the second encoder including a second index generator; receiving a first set of signals representing the k bits of information; dividing the signals into a first part and a second part wherein the first part represents a predetermined number of k 1 bits and the second part represents a predetermined number of k 2 bits; generating a first permutation modulation codeword by applying the first part to the first index generator of the first encoding circuit; generating a second permutation modulation codeword by applying the second part to the second index generator of the second encoding circuit; and combining the first permutation modulation codeword of the first encoding circuit and the second permutation modulation codeword of the second encoding circuit, wherein the combining is based on by a superposition of the first and second permutation modulation codewords. 12. The method of claim 11 , wherein the superposition signaling code has a pin-efficiency of at least 1. 13. The method of claim 11 , wherein the superposition signaling code has a pin-efficiency of at least 1.6. 14. The method of claim 11 , wherein the combining is performed by superimposing currents in wires of a multi-wire communication bus. 15. The method of claim 11 , wherein a number of components of the first vector is equal to a number of components of the second vector. 16. The method of claim 11 , wherein a number of components of the first vector is not equal to a number of components of the second vector. 17. A communication system for transmitting a superpositioning codeword belonging to a superposition signaling code, the communication system comprising: a communication bus with an integer, n, independent signal paths for signal transmission; means for generating a first codeword belonging to a first permutation-modulation codeword set; means for generating a second codeword belonging to a second permutation-modulation codeword set; means for generating the superpositioning codeword representing a sum of the first and second codewords; and means for transmitting the superposition codeword over the communication bus. 18. The communication system of claim 17 , wherein the communication system transmits with a pin-efficiency of 1. 19. The communication system of claim 17 , wherein the communication system transmits with a pin-efficiency of 1.6.

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Classifications

  • Demodulator circuits; Receiver circuits · CPC title

  • Arrangements for coupling common mode signals · CPC title

  • Provision for current-mode coupling · CPC title

  • using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title

  • using multilevel codes · CPC title

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What does patent US9401828B2 cover?
A communication system uses a bus to transmit information, by receiving signals and mapping them to a second set of signals representing codewords of a superposition signaling code, and transmitting the second set of signals. The superposition signaling code can comprise more than one layer. The pin-efficiency can be larger than 1. The system may encode bits into a codeword of a superposition s…
Who is the assignee on this patent?
Cronie Harm, Shokrollahi Amin, Kandou Labs SA
What technology area does this patent fall under?
Primary CPC classification H04L25/0276. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).