Three-Wire Three-Level Digital Interface

Patent metadata

Field	Value
Publication number	US-2016127159-A1
Application number	US-201414892739-A
Country	US
Kind code	A1
Filing date	Jun 17, 2014
Priority date	Jun 17, 2013
Publication date	May 5, 2016
Grant date	—

Abstract

A receiver ( 100 ) for a three-wire digital interface, comprises a first resistive element (R 1 ) coupled between a first input terminal (A) and a first junction node (JA), a second resistive element (R 2 ) coupled between a second input terminal (B) and a second junction node (JB), and a third resistive element (R 3 ) coupled between a third input terminal (C) and a third junction node (JC). A network ( 70 ) comprising first second and third network terminals ( 71, 72, 73 ) is coupled to, respectively, first, second and third junction nodes (JA, JB, JC). The network has substantially the same impedance between all pairs of the first, second and third network terminals. A first comparator (C 1 ) has a non-inverting input ( 10 ) coupled to the first input terminal (A), an inverting input ( 12 ) coupled to the second junction node (JB), and an output ( 14 ) coupled to a first output terminal (AJ). A second comparator (C 2 ) has a non-inverting input ( 20 ) coupled to the AK first input terminal (A), an inverting input ( 22 ) coupled to the third junction node (JC), and an output ( 24 ) coupled to a second output terminal (AK). A third comparator (C 3 ) has a non-inverting input ( 30 ) coupled to the second input terminal (B), an inverting input ( 32 ) coupled to the third junction node (JC), and an output ( 34 ) coupled to a third output terminal (BJ). A fourth comparator (C 4 ) has a non-inverting input ( 40 ) coupled to the second input terminal (B), an inverting input ( 42 ) coupled to the first junction node (JA), and an output ( 44 ) coupled to a fourth output terminal (BK). A fifth comparator (C 5 ) has a non-inverting input (50) coupled to the third input terminal (C), an inverting input ( 52 ) coupled to the first junction node (JA), and an output ( 54 ) coupled to a fifth output terminal (CJ). A sixth comparator (C 6 ) has a non-inverting input ( 60 ) coupled to the third input terminal (C), an inverting input ( 62 ) coupled to the second junction node (JB), and an N output ( 64 ) coupled to a sixth output terminal (CK).

First claim

1 . A receiver for a three-wire digital interface, comprising:
first, second and third input terminals; first, second, third, fourth, fifth and sixth output terminals; first, second and third junction nodes; a first resistive element coupled between the first input terminal and the first junction node; a second resistive element coupled between the second input terminal and the second junction node; a third resistive element coupled between the third input terminal and the third junction node; a network comprising first, second and third network terminals coupled to, respectively, the first, second and third junction nodes the network having substantially the same impedance between all pairs of the first, second and third network terminals; a first comparator having a non-inverting input coupled to the first input terminal, an inverting input coupled to the second junction node, and an output coupled to the first output terminal; a second comparator having a non-inverting input coupled to the first input terminal, an inverting input coupled to the third junction node, and an output coupled to the second output terminal; a third comparator having a non-inverting input coupled to the second input terminal, an inverting input coupled to the third junction node, and an output coupled to the third output terminal; a fourth comparator having a non-inverting input coupled to the second input terminal, an inverting input coupled to the first junction node, and an output coupled to the fourth output terminal; a fifth comparator having a non-inverting input coupled to the third input terminal, an inverting input coupled to the first junction node, and an output coupled to the fifth output terminal; and a sixth comparator having a non-inverting input coupled to the third input terminal, an inverting input coupled to the second junction node and an output coupled to the sixth output terminal.

2 . A receiver as claimed in claim 1 , comprising:
a fourth resistive element coupled between the first network terminal and a common node; a fifth resistive element coupled between the second network terminal and the common node; and a sixth resistive element (R 6 ) coupled between the third network terminal and the common node.

3 . A receiver as claimed in claim 2 , wherein the first, second and third resistive elements have substantially equal resistance, and the fourth, fifth and sixth resistive elements each have a substantially equal resistance in the range 0.33 times to 1.67 times the resistance of the first, second and third resistive elements.

4 . A receiver as claimed in claim 2 , wherein the first, second and third resistive elements have substantially equal resistance, and the fourth, fifth and sixth resistive elements each have a substantially equal resistance in the range greater than 0.67 times the resistance of the first, second and third resistive elements to less than the resistance of the first, second and third resistive elements.

5 . A receiver as claimed in claim 2 , wherein the first, second, third, fourth, fifth and sixth resistive elements have substantially equal resistance.

6 . A receiver as claimed in claim 2 , wherein the first, second and third resistive elements have substantially equal resistance, and the fourth, fifth and sixth resistive elements each have a substantially equal resistance two thirds times the resistance of the first, second and third resistive elements.

7 . A receiver as claimed in claim 1 , comprising:
a seventh resistive element coupled between the first network terminal and the second network terminal; an eighth resistive element coupled between the second network terminal and the third network terminal; and a ninth resistive element is coupled between the third network terminal and the first network terminal.

8 . A receiver as claimed in claim 7 , wherein the first, second and third resistive elements have substantially equal resistance, and the seventh, eighth and ninth resistive elements each have a substantially equal resistance in the range equal to the resistance of the first, second and third resistive elements to five times the resistance of the first, second and third resistive elements.

9 . A receiver as claimed in claim 7 , wherein the first, second and third resistive elements have substantially equal resistance, and the seventh, eighth and ninth resistive elements each have a substantially equal resistance in the range greater than double to less than triple the resistance of the first, second and third resistive elements.

10 . A receiver as claimed in claim 7 , wherein the first, second and third resistive elements have substantially equal resistance, and the seventh, eighth and ninth resistive elements each have a substantially equal resistance three times the resistance of the first, second and third resistive elements.

11 . A receiver as claimed in claim 7 , wherein the first, second and third resistive elements have substantially equal resistance, and the seventh, eighth and ninth resistive elements each have a substantially equal resistance double the resistance of the first, second and third resistive elements.

12 . A signalling signaling system comprising an encoder, a transmitter, a receiver as claimed in claim 1 , and a decoder.

13 . A wireless communication device comprising a signalling signaling system as claimed in claim 12 .

14 . A method of operating a three-wire digital interface, comprising:
providing a receiver as claimed in claim 1 ; establishing voltages at the first, second and third input terminals; and selecting, dependent on the voltages, different output states of the receiver.

15 . A method as claimed in claim 14 , wherein for at least one of the output states two of the first, second and third input terminals are at a common voltage and a third one of the first, second and third input terminals is at a different voltage.

16 . A method as claimed in claim 14 or claim 15 , wherein for at least one of the output states the first, second and third input terminals are at different voltages, wherein one of the first, second and third input terminals is at an intermediate voltage midway between the voltages of the other two of the first, second and third input terminals.

17 . A method of operating a three-wire digital interface as claimed in claim 14 , comprising providing twelve output states of the receiver; wherein for six of the twelve output states two of the first, second and third input terminals are at a common voltage and a third one of the first, second and third input terminals is at a different voltage; and wherein for another six of the twelve output states the first, second and third input terminals are at different voltages with one of the first, second and third input terminals at an intermediate voltage midway between the voltages of the other two of the first, second and third input terminals.

Assignees

• St Ericsson Sa

Inventors

• Koli Kimmo

Classifications

• H04L25/4917 Primary

  using multilevel codes · CPC title

• H04B7/06

  at the transmitting station · CPC title

• H04L25/0292

  Arrangements specific to the receiver end · CPC title

• H04L7/0079

  Receiver details · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title