Transcoding method for multi-wire signaling that embeds clock information in transition of signal state

Patent metadata

Field	Value
Publication number	US-9337997-B2
Application number	US-201414199898-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Mar 7, 2013
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

First claim

What is claimed is:

1. A method for performing multi-wire signaling encoding, comprising:
converting a sequence of data bits into m transition numbers, where m is an integer greater than 1;
converting each transition number into a sequential number from a set of sequential numbers;
converting the sequential number into a raw symbol; and
transmitting the raw symbol via a plurality of differential drivers and spread over n wires, where n is an integer greater than 1, wherein a clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same.

2. The method of claim 1 , wherein converting each transition number into a sequential number from a set of sequential numbers includes converting a plurality of transition numbers into a sequential number.

3. The method of claim 1 , wherein converting the sequential number into a raw symbol includes converting the sequential number into a plurality of raw symbols.

4. The method of claim 1 , where the n wires is greater than or equal to 3.

5. The method of claim 1 , where the n wires is greater than or equal to 4.

6. The method of claim 1 , wherein the raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the n wires.

7. The method of claim 1 , wherein for an n factorial differential signal across pairs of the n wires, r m possible different states are represented by the transition numbers, where r is n!−1.

8. The method of claim 1 , wherein the sequential number is selected from the transition number based on a transition from an immediately previous sequential symbol number.

9. The method of claim 1 , further comprising:
synchronizing raw symbol transmissions using the clock signal.

10. An encoding circuit for performing multi-wire signaling encoding, comprising:
a bits-to-transition number converter for converting a sequence of data bits into m transition numbers, where m is an integer greater than 1;
a transition number-to-sequential number converter for converting each transition number into a sequential number from a set of sequential numbers;
a sequential number-to-raw symbol converter for converting the sequential number into a raw symbol; and
a plurality of differential drivers for transmitting the raw symbol spread over n wires, where n is an integer greater than 1, wherein a clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same.

11. The encoding circuit of claim 10 , wherein converting each transition number into a sequential number from a set of sequential numbers includes converting a plurality of transition numbers into a sequential number.

12. The encoding circuit of claim 10 , wherein converting the sequential number into a raw symbol includes converting the sequential number into a plurality of raw symbols.

13. The encoding circuit of claim 10 , where the n wires is greater than or equal to 3.

14. The encoding circuit of claim 10 , where the n wires is greater than or equal to 4.

15. The encoding circuit of claim 10 , wherein the raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the n wires.

16. The encoding circuit of claim 10 , wherein for an n factorial differential signal across pairs of the n wires, r m possible different states are represented by the transition numbers, where r is n!−1.

17. The encoding circuit of claim 10 , wherein the plurality of differential drivers is equal to n C 2 , where n C 2 =n(n−1)/2.

18. The encoding circuit of claim 10 , wherein the plurality of differential drivers is equal to n.

19. The encoding circuit of claim 10 , wherein the sequential number is selected from the transition number based on a transition from an immediately previous sequential symbol number.

20. An encoding circuit, comprising:
means for converting a sequence of data bits into m transition numbers, where m is an integer greater than 1;
means for converting each transition number into a sequential number from a set of sequential numbers;
means for converting the sequential number into a raw symbol; and
means for transmitting the raw symbol via a plurality of differential drivers and spread over n wires, where n is an integer greater than 1, wherein a clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same.

Assignees

• Qualcomm Inc

Inventors

• Sengoku Shoichiro
• Wiley George Alan
• Lee Chulkyu
• Cheung Joseph

Classifications

• H04L7/027

  extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03K5/1252

  Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title