Thin film transistor substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016126256-A1
Application number	US-201514707287-A
Country	US
Kind code	A1
Filing date	May 8, 2015
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A TFT substrate including a base substrate that includes a plurality of pixel areas; a gate line on the base substrate and extending in a first direction; a data line on the gate line and extending in a second direction; a TFT connected to the gate line and the data line, the TFT including a gate electrode, a semiconductor pattern, and source and drain electrodes, the semiconductor pattern overlapping the gate electrode, the source electrode and the drain electrode overlapping the semiconductor pattern, and the drain electrode being spaced apart from the source electrode; an inorganic insulating pattern covering the data line, the inorganic insulating pattern including an opening aligned with the pixel areas; a shielding electrode overlapping the data line, the shielding electrode on the inorganic insulating pattern; and a pixel electrode on the pixel areas, the pixel electrode being electrically connected to the drain electrode through a first contact hole.

First claim

What is claimed is:

1 . A thin-film transistor substrate, comprising:
a base substrate that includes a plurality of pixel areas; a gate line on the base substrate, the gate line extending in a first direction; a data line on the gate line, the data line extending in a second direction that crosses the first direction; a thin-film transistor connected to the gate line and the data line, the thin-film transistor including:
a gate electrode,
a semiconductor pattern,
a source electrode, and
a drain electrode, the semiconductor pattern overlapping with the gate electrode, the source electrode and the drain electrode overlapping with the semiconductor pattern, and the drain electrode being spaced apart from the source electrode;
an inorganic insulating pattern covering the data line, the inorganic insulating pattern including an opening aligned with the pixel areas; a shielding electrode overlapping with the data line, the shielding electrode being on the inorganic insulating pattern; and a pixel electrode on the pixel areas, the pixel electrode being electrically connected to the drain electrode through a first contact hole.

2 . The thin-film transistor substrate as claimed in claim 1 , wherein the inorganic insulating pattern has a thickness of about 8,000 Å to about 10,000 Å.

3 . The thin-film transistor substrate as claimed in claim 1 , wherein the inorganic insulating pattern includes silicon oxide or silicon nitride.

4 . The thin-film transistor substrate as claimed in claim 1 , further comprising a gate insulating layer covering the gate line and the gate electrode.

5 . The thin-film transistor substrate as claimed in claim 4 , wherein the gate insulating layer has a thickness of about 3,000 Å to about 5,000 Å.

6 . The thin-film transistor substrate as claimed in claim 1 , further comprising a passivation layer covering the shielding electrode and the thin-film transistor.

7 . The thin-film transistor substrate as claimed in claim 6 , wherein the passivation layer has a thickness of about 1,000 Å to about 3,000 Å.

8 . The thin-film transistor substrate as claimed in claim 1 , wherein the shielding electrode includes a material that is substantially the same as that of the pixel electrode.

9 . The thin-film transistor substrate as claimed in claim 8 , wherein the shielding electrode and the pixel electrode include indium tin oxide, indium zinc oxide, or aluminum-doped zinc oxide.

10 . The thin-film transistor substrate as claimed in claim 8 , wherein the shielding electrode and the pixel electrode are formed on different layers.

11 . The thin-film transistor substrate as claimed in claim 1 , wherein the pixel electrode has a slit pattern.

12 . The thin-film transistor substrate as claimed in claim 1 , further comprising:
a gate pad electrode connected to the gate line; a gate insulating layer on the gate pad electrode; a passivation layer on the gate insulating layer; and a bridge electrode on the passivation layer, wherein the bridge electrode is electrically connected to the gate pad electrode through a second contact hole.

13 . The thin-film transistor substrate as claimed in claim 1 , further comprising a common electrode overlapping with the pixel electrode.

14 . A method of manufacturing a thin-film transistor substrate, the method comprising:
forming a gate pattern on a base substrate, the base substrate including a plurality of pixel areas, the gate pattern including a gate line and a gate electrode, and the gate line extending in a first direction; forming a data pattern such that the data pattern includes a data line, a source electrode, and a drain electrode, the data line extending in a second direction that crosses the first direction, the source electrode and the drain electrode overlapping with the gate electrode, and the drain electrode being spaced apart from the source electrode; forming an inorganic insulating layer by depositing an inorganic insulating material on the base substrate; forming a shielding electrode on the inorganic insulating layer by using a photo pattern as a mask such that the shielding electrode overlaps with the data line; forming an inorganic insulating pattern that covers the data line by etching the inorganic insulating layer such that etching of the inorganic insulating layer includes using the photo pattern and the shielding electrode as a mask; forming a passivation layer by depositing the inorganic insulating material on the base substrate such that the passivation layer covers the shielding electrode, the source electrode, and the drain electrode; forming a first contact hole by etching the passivation layer such that the first contact hole exposes the drain electrode; and forming a pixel electrode that is electrically connected to the drain electrode through the first contact hole.

15 . The method as claimed in claim 14 , wherein the inorganic insulating layer is formed with a thickness of about 8,000 Å to about 10,000 Å.

16 . The method as claimed in claim 14 , wherein the inorganic insulating material includes silicon oxide or silicon nitride.

17 . The method as claimed in claim 14 , further comprising forming a gate insulating layer by depositing the inorganic insulating material on the base substrate such that the gate insulating layer covers the gate pattern.

18 . The method as claimed in claim 17 , wherein the gate insulating layer is formed with a thickness of about 3,000 Å to about 5,000 Å.

19 . The method as claimed in claim 14 , wherein the passivation layer is formed with a thickness of about 1,000 Å to about 3,000 Å.

20 . The method as claimed in claim 14 , wherein:
the gate pattern includes a gate pad electrode connected to the gate line, and the method further includes: forming a gate insulating layer on the gate pad electrode; forming a passivation layer on the gate insulating layer; forming a second contact hole by etching the gate insulating layer and the passivation layer such that the second contact hole exposes the gate pad electrode; and forming a bridge electrode that is electrically connected to the gate pad electrode through the second contact hole.

Assignees

• Samsung Display Co Ltd

Inventors

• Hwang Tae-Hyung
• Kim Won-Ho
• Lim Seong-Su

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/6711 Primary

  by using electrodes contacting the supplementary regions or layers · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title